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electrical_engineering_and_electronics_1:block08 [2025/10/24 19:48] – mexleadminelectrical_engineering_and_electronics_1:block08 [2026/01/10 13:02] (aktuell) – mexleadmin
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 On the {{https://en.wikipedia.org/wiki/Network_analysis_(electrical_circuits)|wiki page for network analysis}}  the different methods are described very well in a compact way </callout> On the {{https://en.wikipedia.org/wiki/Network_analysis_(electrical_circuits)|wiki page for network analysis}}  the different methods are described very well in a compact way </callout>
  
-===== Learning objectives =====+===== 8.0 Intro ===== 
 + 
 +==== 8.0.1 Learning Objectives ====
 <callout> <callout>
   * Define **terminal** and **port**; distinguish **one-port** (two-terminal) vs. **two-port** views; identify input/output variables $(U,I)$ at a port.   * Define **terminal** and **port**; distinguish **one-port** (two-terminal) vs. **two-port** views; identify input/output variables $(U,I)$ at a port.
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 </callout> </callout>
  
-===== 90-minute plan =====+~~PAGEBREAK~~ ~~CLEARFIX~~ 
 +==== 8.0.2 Preparation at Home ==== 
 + 
 +And again:  
 +  * Please read through the following chapter. 
 +  * Also here, there are some clips for more clarification under 'Embedded resources'.  
 + 
 +For checking your understanding please do the following exercise: 
 +  * 4.5.3 
 + 
 +==== 8.0.3 90-minute plan ====
   - Warm-up (8 min):   - Warm-up (8 min):
     - Quick quiz on passive/active sign convention and $P=U\cdot I$ (from Block 07).     - Quick quiz on passive/active sign convention and $P=U\cdot I$ (from Block 07).
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     - Summary table (when to use which method); minute paper: “One thing I can now do, one question I still have.”     - Summary table (when to use which method); minute paper: “One thing I can now do, one question I still have.”
  
- +==== 8.0.4 Conceptual Overview ====
-===== Conceptual overview =====+
 <callout icon="fa fa-lightbulb-o" color="blue"> <callout icon="fa fa-lightbulb-o" color="blue">
   - **Port thinking:** Draw a virtual cut around the “rest of the world”. At that boundary (two terminals), everything inside looks like an equivalent **linear source** (Thevenin/Norton) to everything outside.   - **Port thinking:** Draw a virtual cut around the “rest of the world”. At that boundary (two terminals), everything inside looks like an equivalent **linear source** (Thevenin/Norton) to everything outside.
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 ~~PAGEBREAK~~ ~~CLEARFIX~~ ~~PAGEBREAK~~ ~~CLEARFIX~~
  
-===== Core content =====+===== 8.1 Core content =====
  
-==== Two-Terminal Theory / One-Port Theory ====+==== 8.1.1 Two-Terminal Theory / One-Port Theory ====
  
 <WRAP right> <imgcaption imageNo1 | examples for networks> </imgcaption> {{drawio>electrical_engineering_and_electronics_1:TwoPoleTheory01.svg}} </WRAP> <WRAP right> <imgcaption imageNo1 | examples for networks> </imgcaption> {{drawio>electrical_engineering_and_electronics_1:TwoPoleTheory01.svg}} </WRAP>
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-====  Superposition Principle ====+==== 8.1.2  Superposition Principle ====
  
 The superposition principle shall first be illustrated by some examples: The superposition principle shall first be illustrated by some examples:
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 ~~PAGEBREAK~~ ~~CLEARFIX~~ ~~PAGEBREAK~~ ~~CLEARFIX~~
-===== Common pitfalls =====+===== 8.2 Common Pitfalls =====
   * **Deactivating sources incorrectly:** replacing an ideal voltage source with an **open** (instead of a short), or an ideal current source with a **short** (instead of an open).   * **Deactivating sources incorrectly:** replacing an ideal voltage source with an **open** (instead of a short), or an ideal current source with a **short** (instead of an open).
   * **Superposing powers:** only **$u$** and **$i$** superpose; $P$ does not. Compute powers **after** summing.   * **Superposing powers:** only **$u$** and **$i$** superpose; $P$ does not. Compute powers **after** summing.
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   * **Ignoring loading:** using the unloaded divider ratio $\dfrac{R_2}{R_1+R_2}$ while a finite $R_{\rm L}$ is attached → systematic voltage error.    * **Ignoring loading:** using the unloaded divider ratio $\dfrac{R_2}{R_1+R_2}$ while a finite $R_{\rm L}$ is attached → systematic voltage error. 
      
-===== Exercises =====+===== 8.3 Exercises =====
  
-==== Longer exercises ====+==== Longer Exercises ====
  
 #@TaskTitle_HTML@#4.5.1 Converting a bipolar signal to a unipolar signal <fs medium>(HARD, not from written test)</fs>#@TaskText_HTML@# #@TaskTitle_HTML@#4.5.1 Converting a bipolar signal to a unipolar signal <fs medium>(HARD, not from written test)</fs>#@TaskText_HTML@#