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introduction_to_digital_systems:at_the_heart_of_a_computer [2022/04/27 13:53]
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| ~~PAGEBREAK~~ ~~CLEARFIX~~ | |
| ==== zwei Transistor(typ)en reichen ==== | |
| <WRAP right><well> | |
| <imgcaption pic4|n- und p-Kanal MOSFETs></imgcaption> \\ | |
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| {{url>https://www.falstad.com/circuit/circuitjs.html?running=false&ctz=CQAgjCAMB0l3BOJyWoVaYDsYAcuA2BAJgFZdjcEBmSgkAFlJGYeoCgAzES3cBhiGrV6YAS2IZmMSMXYAlISJ74l9MvUhRGW6dpil2AczXgs9YaJJQFZ0eLCV+giJLDwe0ZsS-7oDBHYAdztncGsxQTkQy3ACLVjsTXYGSGo4rTBHFT5I7WoAfTACyCLiYgQGAtIS2Dhi0uICwo5uXiFIQVjqTpZ0rRlonlJ7KNU8yGNTWgTlalJJScVEp1iETW1Uln0pYOHR-Y7BSZCNI5zzyYAPIQJ1HBZIPmIsQRc+AAcAWgBpAEMAHZ-AA2AB0AM4AWQA8gBlABiAFEACrsG7ULDpSosMDMBBYRjgPgA36AkEQmEIlFolTMMB3HhIOLod4gADiNPatGYPUktD4rI56KYcR5pAJ9IFRJAsJp1BFFQS4sZ6VZsuFdPlQmVYAxhLwIAAInLxLQCfMLD19XxjZDQnkkhltD5DCEwBFxGcJuwgA 600,500 noborder}} | |
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| </well></WRAP> | |
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| Ok, now we know at least that the chip consists of many transistors. But how do they work and how can you build something as complex as a processor from them? The exact function is the content of the course '(Analog) [[circuit_design:start|Circuit Design]]'. For digital applications it is sufficient to have a simple picture of a certain type of transistor - the MOSFET - in your head. This has the three terminals: | |
| * **S**ource ("Quelle"), the inflow of charge carriers | |
| * **D**rain ("Senke"), the outflow of the charge carriers | |
| * **G**ate ("Tor"), the gatekeeper, which regulates the passage between source and drain: If the correct voltage gate is present at the gate terminal ((to be correct: the voltage has to be between gate and source an, not at the gate terminal...)), the Source and Drain terminals are short-circuited, that is, a current can flow and the voltage drop between them becomes small. | |
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| Two types of MOSFET are important in the following digital circuits: | |
| * one that is __non-conductive__ for __low voltages__ ($0V$, logic $0$, Low, $L$, or False) at the gate (n-channel MOSFET) and | |
| * one that is __non-conductive__ for __high voltages__ ($5V$, logic $1$, High, $H$ or True) at the gate (p-channel MOSFET). | |
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| In the picture on the right (<imgref pic4>) you can see the two variants in action, when the voltage at the gate just assumes the digital voltage values. | |
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| ~~PAGEBREAK~~ ~~CLEARFIX~~ | |
| Now it is interesting, that these two kinds of transistors are sufficient to build all variants of logical functions. Logical functions combine one or more inputs ($X_1, ... X_n$) in such a way, that every kind of input uniquely leads to an output ($Y_1, ... Y_n$). In circuits, so-called gates correspond to logical functions. They need not be only such simple functions like an AND-gate. Mathematical operations can also be mapped in this way. To do this, gates must be cleverly combined with each other. In an exercise on binary logic, it is shown that all gates can be constructed using NAND or NOR gates. So, if we could figure out how to build a NAND or NOR gate from transistors, we could in turn build all gates up to addition from it. | |
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| ==== Gatter logisch? ==== | |
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| <WRAP right><well> | |
| <imgcaption pic20|Simulation eines Inverters></imgcaption> \\ | |
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| {{url>https://www.falstad.com/circuit/circuitjs.html?running=false&ctz=CQAgjCAMB0l3EwwEx2QdnQZkgDmQGwCcR6IyuIArNZAFABmIWuALM5O61sh+wZCjQCQyMjoBzEN149BM5lV70AStJ4giIha0qD5gmvqFU6arAUphW7HO2v3y5OOWg1kb5tGtgqRQlRYVLikRFhCunQA7syW4DbMbPHs9DEWVgnp5OjK0eq8yMhcWuRFUIyJ9gkKDiAEEAC0MCIwYnSskOFy4GCySbWCWAD6BKxDkEO9yERjVOOwCONDyEPDWHQAstIlhexUCbtQrqYd4ayj4P7UFKUpmiNjE6xIK3MwYEtgeQolNTep+XAAkBhwBCkO4NwejyWQwsjidnKaQRnEqfCRPVkqNqiIBYF62V4+KxKTyYGBh3JgjhGKp4HQIjpoLJwJKdOJ5S2h25HVuRw8phiTLK3LKeIJtQ5NPFRISkoSqkxyTqVUcBRcAuOXh8fgCQRC6DCEVwZiBgjZwN0RwM1GtJkkZuYFkdQVyviIjo57IZ4Gc4HgAfgdHdjppdKwzupgiQgYDdAAHtc6pdeB72GUALYASwALgAdADOAGUAMYACwAhgAbHMAUwATgA7BPkXA0PbOsjp9jZ-MFgDCGwA8kWGgAVesVxsFrMFnMAe3rtebQA 600,500 noborder}} | |
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| </well></WRAP> | |
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| Before the NAND gate is considered, a very simple circuit is to build, which generates the output value $Y(0)=1$ from the digital input value $X=0$ and for $X=1$ correspondingly $Y(1)=0$. This circuit always negates the input value and is called inverter. For this purpose the two types of transistors are combined similar to a voltage divider or a half bridge. Thus, only one transistor (TRANSfer ResISTOR) becomes conductive at a time, the other one correspondingly high impedance. | |
| In <imgref pic20> the corresponding circuit with normally open and normally closed switch is also drawn. It is important for the following consideration that the logic voltages ($0V$, $5V$) are just switched complementary via the switches. For this reason this technique is also called CMOS technique: __C__omplementary __MOS__FET. In today's electronics, this technology is used throughout and has completely replaced older variants (e.g. TTL). | |
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| ~~PAGEBREAK~~ ~~CLEARFIX~~ | |
| <WRAP><well> | |
| <imgcaption BildNr1 | Inverter gate in CMOS on chip> | |
| </imgcaption> | |
| {{drawio>InverterGatterMikroskop}} | |
| </well></WRAP> | |
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| From this example, it can be seen how a logical $1$ can become $0$ in mobile phones, vehicle control units, and television sets. The <imgref BildNr1> shows the realization of this gate in silicon: | |
| * Figure (1) shows the image of a scanning electron microscope, which shows several layers at the same time. The three circular elements are electrical passages ("vias") through several layers. In green are the two structures of the MOSFETs, which can act as a "valve" to open the connection up ($5V$) or down ($0V$). | |
| * Figure (2) is a false color image. In beige is the top conductive layer and in blue is the non-conductive region of the top layer. | |
| * In figure (3), the different signals have been highlighted. \\ The output $A$ is taken out via a via with the right connection. | |
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| ~~PAGEBREAK~~ ~~CLEARFIX~~ | |
| ==== not-AND, or? ==== | |
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| <WRAP right><well> | |
| <imgcaption pic21|Simulation of a CMOS NAND gate></imgcaption> \\ | |
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| {{url>https://www.falstad.com/circuit/circuitjs.html?running=false&ctz=CQAgDOB0YzBMICMZJ3gdnQZjADjgGwCcR6IcuIArNWAFABmIWazVCWBlW7IBEKAlDBxGzVhW5dyuSvyhCUIugHdm0xIg4aALDvCr1lODoidj6BPQDmRu+ZCmBdAEp2dUygPCOINbyhUrkh6IERC4WFCiOTkMOSQNHCJzJCIOohURIRUPLikRFhQHsHp+ojykRUQMQjIEMlJKVhp6AQ6JHBYuARw4ehEXomGZVHklmP0anATkSwQkVPjCJEzHKxLo9XMYOXySzh7ZqzbB7tI8ofkpgZqDiYQHUIPBkwZEUI67WMEMQC0gmEoiY8zGDkivxAAMgimgolMRS0cn0cCoHx8BAA+u1MWBMVo+jpMVRcdAYIhcZi4NjMVg6AikBRGcY0RdvOhsUS8RkRMTSbAwKQCGjUZTqRy6QBZaihF78Yw3BrDBl6Yx4ahta7eRBETmUnnUkkoCl4xCGByITX3RXmk7yd5s26OCqOh2Lc3SDx2XDOO6eyhffRepaBxwB74+p2hzQIaOakPfS1CC3xj2UUYpxSGJ5amUom1+7jnBxYThOq4vCuycvnSTiBrVpZrevLNhWQzNnjrMy8ejSrbyLbxhJBfuhKqhGM+Rp0AAeIGrmCQ50j+ZAAEE5wvojoaMg6l61wAhLdZIpwdJ8QXkS2Oa4gACadGlDr+kVVUMWI63XzIfy0MQeEU-6IAG95PncuD6G+nwujBBhuM2fyRqiQjITUsRoEqTQ0C06SZNkwp5AURQoCUiETCBCCoVCU61Mu2EjqkSYdNk3S9P0gxQEE0yUZGVzoU6SFTgJU59q2glIV+M7SsJWgSUi07DPOF5EJ+548J+jz3puKk6rRJjkJp-4XnehknpkMQCXMUGfoosQ0EEQA 600,500 noborder}} | |
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| </well></WRAP> | |
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| But how does the NAND gate work, on which logic can be built it? The concept behind this gate is that the output will only output logic false ($Y=0$) if both inputs are set to logic true ($A=1$ and $B=1$). The gate is shown in <imgref pic21> above. This must be implemented using the two types of transistors , which were already explained. So, this structure must be built in such a way that: | |
| - only if both inputs switch transistors with $A=1$ and $B=1$ at the same time, $0V$ shall be applied, | |
| - if one of the inputs $A$ or $B$, or both equal 0, $5V$ shall be applied. | |
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| The first one is possible via a series connection of transistors at $0V$. These must short the source and drain terminals at a gate voltage of $5V$ (input to logic $1$), so n-channel MOSFETs are required. \\ | |
| The second one requires a parallel connection of transistors against $5V$. These must short the source and drain with a gate voltage of $0V$. Here p-channel MOSFETs are used (<imgref pic21> below). | |
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| The implementation in silicon (<imgref BildNr2>) again appears somewhat unclear at first glance. In this figure three pictures are to be seen, again. In the first picture the transistors are marked green again and also the vias are to be recognized again over white circles. If you take a closer look at the diagram, you will notice that the via at $5V$ can be reached via the left or right MOSFET. However, the via at $0V$ can only be reached if both lower MOSFETs short-circuit. Thus, the structure is consistent with the circuit determined so far. The <imgref pic7> and <imgref pic22> should show this in more details. | |
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| ~~PAGEBREAK~~ ~~CLEARFIX~~ | |
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| <WRAP right> | |
| <WRAP group><WRAP column> | |
| <WRAP right><well> | |
| <imgcaption BildNr2 | NAND-Gatter in CMOS auf Chip> | |
| </imgcaption> | |
| {{drawio>NANDGatterMikroskop}} | |
| </well></WRAP> | |
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| <imgcaption pic7|>{{ grundlagen_der_digitaltechnik:cmos_nand_schematic.gif|NAND Gate in CMOS auf Chip (schematisch)}}</imgcaption> | |
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| </WRAP><WRAP column> | |
| <well> | |
| <imgcaption pic22|Simulation eines CMOS NAND-Gatters (Struktur ähnlich Si-Die)></imgcaption> \\ | |
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| {{url>https://www.falstad.com/circuit/circuitjs.html?running=false&ctz=CQAgDOB0YzCMI5kgJhig7BgzGAHCgGwCcxGIKArCNZWAFADmFeeI2hbKrIALHIXD0ASnzaVu7FDUkJpaCCkjUl1bJDj9KxIpWyU8ZYtii88IsX0K8pVm3MQwKy52o0ZrpFNjyEUxQgxiNmRKegB3Swk2XmsZEPpeMBM8CF4Ainx48EQAfWtcsFy4FH9eXMpC6HhC3JRi3OxE5JBUvmx5LNibRXzyov4wesrkWDAyQko-EbrZpoBZCiSpNLYOiEVlZpTFHjQ1tBzCPtrB4aq4WrgI9g5EXhsONk0em6f7mySIF6FI7Dv3oDOL92MD3l9QQlIrwOpCxBB3gxItw1mCwI9gQxRLhPmt0TkNnwINRCaE3vizO1pJSkVTLDDpD9aTjLCymW9DnAdCsKChXtCBBQpnxBesQfxBFzqYL9uKZV0ZXzxTE4vpqXFmYcqIIxWLmcCfu8SlClgjDmYzRsbhaeTbEfRFpTolESjlVA76XFKQ8Qq56AAzHn-HWHd4SRAuUYoAMikNpUXA8NwSPQaOBsVSnk-PQRkmpjmWoN3BiBiWIbll7MmZN5ob0AAeIAAtLQ4NQ4AhKHAYksQABBBvN6i8JMIEfD3sAITeBskfO+klp88yXGWepuy9ly+N4rizu6pt3NmXDMPzLuy7VZ7e4cv4YPDEbTdDVHYZp7SoA8gBVAAq1plYVT2XWlgOWMtSn5HlINuQQQLeC81y1YUGDbBAIDaTDCWkYlBybPBaGkJsSBoCclWnJ8CNaExiOIVpBGPGwB0WJtYTiVjqV9d0WNhDIONabCtkifiNRADUbn4jIICkiwRJsJtKTiBwkE2FQXHUOAPHSHQfD8AIghCLZREkwQFLYDIHAUVxrI0rQdEmfRDCCExkDMG4sMQV02lpDtpDaXzm0FHzXSbQUzMCwRH0CylQoQJtgmbD8bB-f8WJisK2lCyK-SAA 600,600 noborder}} | |
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| </well> | |
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| </WRAP></WRAP></WRAP> | |
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| ~~PAGEBREAK~~ ~~CLEARFIX~~ | |
| ==== eine einfache Rechnung ==== | |
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| <WRAP right><well> | |
| <imgcaption pic24|Simulation eines Addierers></imgcaption> \\ | |
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| {{url>https://www.falstad.com/circuit/circuitjs.html?running=false&ctz=CQAgjCAMB0l3BWcMBMcUHYMGZIA4UA2ATmIxAUgpABZsAoMBCFGqsDQkbNcTqECmoJ6AGT5d2-ALTFJAgGYBDADYBnAKbVIYwWxBy9VWfKrL1WpDoCyFGjQl2HJgSmgimEbNi4cuNMF9+KiEqEQB3bh9wYiFvIMl6SPjwQioUvygkqITuXkydTxyQPCoArlLXYWzWdljBfBjQ7MzAkP02rNsEGUCKGUMQ90ZmYuk+8pBx+SEkD1G6IWmKMCW+kIEI2h4pncWp9ez95cnlnUj9sp3K8+2hSsmb7Iy04sIHW5T3sZ3bycyECg8I5PtFDLUDIlImhgeDGmB6qD5AUspEUa1XrdmGsuD0uGdsgh7I5AcCCjV9HDYYkAB4NJZ4YiCPrSPD+PQgAA6AAd6HTKBBZGEmFM8OQHKwuQBHegAI3AxOk3zS5BQKGwWTpYDZU2JaCWAVoHIAgnzBJRdRLCPjDRKHAAhM0IUbSGizQjA6TYJl2kAAYSdeCQro1aUF+l9AGVGMQkClxvU2MYEc1xPGU4I8J6M1QzKpNNpdOnXkDs5jwCBzAWrPRbMcMzRKgnQoJhnWdtMyk3OkMREA 600,500 noborder}} | |
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| </well></WRAP> | |
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| Wie können nun die NAND-Gatter so verschaltet werden, dass das Rechenwerk Operationen wie $y=a+b$ durchführen kann? Dazu wird die Operation zunächst nur für binäre Werte betrachtet. Um die binäre Größen von dezimalen Größen zu unterscheiden wird diesen ein $0b$ vorangestellt. Folgende Kombinationen sind also möglich: | |
| * $0 + 0 = 0$ bzw. $0b0 + 0b0 = 0b00$ | |
| * $0 + 1 = 1$ bzw. $0b0 + 0b1 = 0b01$ | |
| * $1 + 0 = 1$ bzw. $0b1 + 0b0 = 0b01$ | |
| * $1 + 1 = 2$ bzw. $0b1 + 0b1 = 0b10$ | |
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| Es ist zu sehen, dass nur wenn beide Eingänge gerade $1$ sind die zweite Stelle des Bitwertes gesetzt ist. Dies entspricht gerade einem AND. Da aber alles aus NAND-Gattern aufgebaut werden soll, muss eine geschickte Zusammenschaltung dieser Gatter gefunden werden. Hierzu wird einem NAND-Gatter ein Inverter-Gatter nachgeschalten. Das Inverter-Gatter wiederum erhält man über ein NAND-Gatter, wenn beide Eingänge verbunden werden. In <imgref pic24> ist diese Schaltung unten durch die beiden unteren NAND-Gatter dargestellt. \\ Auch für die erste Stelle des Bitwertes lässt sich eine Schaltung finden. Wie kann man auf diese Schaltungen kommen? Dies wird im Kapitel [[Schaltnetze]] erklärt. | |
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| ~~PAGEBREAK~~ ~~CLEARFIX~~ | |
| Werden viele Eingänge oder Ausgänge zusammengefasst, können größere Zahlenwerte umgesetzt werden. Das heißt, die Rechnung $3+3$ bzw. im binären $0b\color{green}1\color{violet}{1} + 0b\color{blue}{1}\color{red}{1}$ wird auf mehrere Einzelrechnungen heruntergebrochen. Dies ähnelt der händischen Addition durch Untereinanderschreiben der Zahlenwerte und schrittweiser Rechnung. In diesem Beispiel müsste zunächst $0b\color{violet}{1} + 0b\color{red}{1}$ berechnet werden, was $0b\boldsymbol{1}0$ ergibt. Im nächsten Schritt $0b\color{green}1 + 0b\color{blue}{1}$ muss zusätzlich noch der Überlauf aus der vorherigen Rechnung $0b\boldsymbol{1}$ berücksichtigt werden. So können prinzipiell beliebig lange Zahlen miteinander verknüpft werden. | |
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| Um die Zahlen handhabbarer für Mensch und Maschine zu gestalten wurde eine sinnvolle Gruppierung eingerichtet: 8 binäre Zahlenwerte werden zu einem Byte zusammengefasst. Dieses kann für Menschen lesbar als Dezimalwert $0...255$ oder Hexadezimalwert $0x00 ... 0xFF$ in Programmen dargestellt werden. Im Microprozessor werden diese Zahlenwerte stets als Binärwert gehandhabt. | |
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| ~~PAGEBREAK~~ ~~CLEARFIX~~ | |
| ==== Nano-Lego ==== | |
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| <imgcaption pic10|>{{ https://upload.wikimedia.org/wikipedia/commons/a/aa/Silicon_chip_3d.png?300|dreidimensionale Struktur eines Silizium Chips}}</imgcaption> | |
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