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introduction_to_digital_systems:boolean_algebra [2023/03/27 10:17]
mexleadmin 		introduction_to_digital_systems:boolean_algebra [2023/09/19 23:44] (aktuell)
mexleadmin
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-====== 1. Boolean Algebra ======+====== 1 Boolean Algebra ======
  
 ===== 1.1 Motivation: Digital Electronics in Daily Life ===== ===== 1.1 Motivation: Digital Electronics in Daily Life =====
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   - apply the Boolean rules of arithmetic.   - apply the Boolean rules of arithmetic.
   - simplify Boolean expressions.   - simplify Boolean expressions.
-  - understand the following terms: bit, the different (logic) gates, timing diagram, truth table.+  - understand the following terms: bit, the different (logic) gates, timing diagram, and truth table.
   - understand the purpose of the Tri-State gate and the "Z" state.   - understand the purpose of the Tri-State gate and the "Z" state.
   - understand the use of the "Don't care" state.   - understand the use of the "Don't care" state.
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 We have already learned about the 'bit', and its two-valued value. This can be connected to the ancient idea of binary logic.  We have already learned about the 'bit', and its two-valued value. This can be connected to the ancient idea of binary logic. 
-The Greek Philosopher Aristotle started to build up a system in order to conclude from statements like "at night, it is dark outside" and "it is night" to "it has to be dark outside".+The Greek Philosopher Aristotle started to build up a system to conclude from statements like "at night, it is dark outside" and "it is night" to "it has to be dark outside".
 It might seem a bit unrelated to controllers and computers, at the first sight. But in this scientific interpretation of logic, all logic statements are either true or false. It might seem a bit unrelated to controllers and computers, at the first sight. But in this scientific interpretation of logic, all logic statements are either true or false.
  
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 ~~PAGEBREAK~~ ~~CLEARFIX~~ ~~PAGEBREAK~~ ~~CLEARFIX~~
  
-In order to control an (output) voltage with an (input) voltage two complement types of switches are combined similar to a voltage divider or a half-bridge (see <imgref pic21>). One is normally open and the other one is normally closed. This can also be set up with complementary types of transistors. Thus, only one transistor (TRANSfer ResISTOR) becomes conductive at a time, the other one correspondingly high impedance.+To control an (output) voltage with an (input) voltage two complement types of switches are combined similar to a voltage divider or a half-bridge (see <imgref pic21>). One is normally open and the other one is normally closed. This can also be set up with complementary types of transistors. Thus, only one transistor (TRANSfer ResISTOR) becomes conductive at a time, the other one correspondingly high impedance.
  
 With this setup, the logic voltages ($0~\rm V$, $5~\rm V$) are just switched complimentary via the switches. This technique is also called **CMOS** technique: __C__omplementary __MOS__FET. In today's electronics, this technology is used throughout and has completely replaced older variants (e.g. TTL). With this setup, the logic voltages ($0~\rm V$, $5~\rm V$) are just switched complimentary via the switches. This technique is also called **CMOS** technique: __C__omplementary __MOS__FET. In today's electronics, this technology is used throughout and has completely replaced older variants (e.g. TTL).
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 Besides the symbol other representation are also common (see also <imgref BildNr07>): Besides the symbol other representation are also common (see also <imgref BildNr07>):
-  * The **truth table** shows the input(s) $X$ on the left and the output(s) $Y$ on the right. There is a row for each distinct combination of inputs. This representation will get handy in the next chapters, in order to analyze more complex logic. Often instead they are also called **look-up table** or **LUT**.+  * The **truth table** shows the input(s) $X$ on the left and the output(s) $Y$ on the right. There is a row for each distinct combination of inputs. This representation will get handy in the next chapters, to analyze more complex logic. Often instead they are also called **look-up table** or **LUT**.
   * The **timing diagram** shows the sequential behavior. For this diagram, the input variables are stimulated with all possible state combinations. Also, this will become handy, especially in the chapter [[Sequential Logic]].   * The **timing diagram** shows the sequential behavior. For this diagram, the input variables are stimulated with all possible state combinations. Also, this will become handy, especially in the chapter [[Sequential Logic]].
   * In **math** the inversion has also multiple representations e.g.   * In **math** the inversion has also multiple representations e.g.
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 ~~PAGEBREAK~~ ~~CLEARFIX~~ ~~PAGEBREAK~~ ~~CLEARFIX~~
  
-The next circuit will generate a positive output only, if __all__ inputs are true. This is called a logical **__con__junction** ([[https://en.wikipedia.org/wiki/logical_conjunction|logic AND]], [[https://en.wikipedia.org/wiki/AND_gate|AND gate]]). When one or more inputs are false the output is also false. <imgref pic22> shows an example: The light is only on ($Y=1$), when all inputs are on ($X0=1$, $X1=1$, ...). This is commonly used for safety circuits, e.g. when the workspace of a robot has multiple doors and all have to be closed in order to start.+The next circuit will generate a positive output only, if __all__ inputs are true. This is called a logical **__con__junction** ([[https://en.wikipedia.org/wiki/logical_conjunction|logic AND]], [[https://en.wikipedia.org/wiki/AND_gate|AND gate]]). When one or more inputs are false the output is also false. <imgref pic22> shows an example: The light is only on ($Y=1$), when all inputs are on ($X0=1$, $X1=1$, ...). This is commonly used for safety circuits, e.g. when the workspace of a robot has multiple doors and all have to be closed to start.
  
 <WRAP center>  <WRAP center> 
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 ~~PAGEBREAK~~ ~~CLEARFIX~~ ~~PAGEBREAK~~ ~~CLEARFIX~~
  
-The NOT gate is often used in front of or after other gates. When used after AND gates, this creates a 'NOT AND' or in short 'NAND' ([[https://en.wikipedia.org/wiki/Sheffer_stroke|logic NAND]], [[https://en.wikipedia.org/wiki/NAND_gate|NAND gate]]). This circuit will only generate a negative output only, if __all__ inputs are true. When one or more inputs are false the output is true. <imgref pic25> shows an example: The light is only off ($Y=0$), when all inputs are high ($X0=1$, $X1=1$, ...). In the simulation one has to look in detail: the used switches are normally closed (closed when the input is low). Therefore the switches are only open when the input is high.+The NOT gate is often used in front of or after other gates. When used after AND gates, this creates a 'NOT AND' or in short 'NAND' ([[https://en.wikipedia.org/wiki/Sheffer_stroke|logic NAND]], [[https://en.wikipedia.org/wiki/NAND_gate|NAND gate]]). This circuit will only generate a negative output, if __all__ inputs are true. When one or more inputs are false the output is true. <imgref pic25> shows an example: The light is only off ($Y=0$), when all inputs are high ($X0=1$, $X1=1$, ...). In the simulation one has to look in detail: the used switches are normally closed (closed when the input is low). Therefore the switches are only open when the input is high.
  
 <WRAP center>  <WRAP center> 
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 </WRAP> </WRAP>
  
-The circuit symbols are shown in <imgref pic26>. In order to shorten the circuit, the NOT is often 'shrank' only to a small circle after the gate.+The circuit symbols are shown in <imgref pic26>. To shorten the circuit, the NOT is often 'shrank' only to a small circle after the gate.
  
 <WRAP center> <WRAP center>
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 <callout title="Example of an Application for a Tri-State Gate"> <callout title="Example of an Application for a Tri-State Gate">
  
-Let's imagine, we want to connect two microcontroller $A$ and $B$ in order to enable a communication, i.e. transmitting and receiving data on both sides. \\ +Let's imagine, we want to connect two microcontrollers $A$ and $B$ to enable communication, i.e. transmitting and receiving data on both sides. \\ 
-One posibility would be to use two wires:+One possibility would be to use two wires:
   * One wire for data sent from $A$ to $B$   * One wire for data sent from $A$ to $B$
   * One wire for data sent from $B$ to $A$   * One wire for data sent from $B$ to $A$
-This is shown in <imgref pic910>. You can change the inputs $X0$ and $X1$ by clicking on the ''L'' and ''H'' nearby this labels. \\ +This is shown in <imgref pic910>. You can change the inputs $X0$ and $X1$ by clicking on the ''L'' and ''H'' nearby these labels. \\ 
-The big advantage of this configuration is, that both connected microcontroller can send data whenever they want. The biggest disadvantage is, that one need two wires.+The big advantage of this configuration is, that both connected microcontrollers can send data whenever they want. The biggest disadvantage is, that one needs two wires.
  
 <WRAP><well> <WRAP><well>
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 Once we think of only using one wire, it becomes more complicated: a single wire can only be driven by one digital input - only one can transmit data at any given time.  Once we think of only using one wire, it becomes more complicated: a single wire can only be driven by one digital input - only one can transmit data at any given time. 
-Therefore, we have to switch on both sides from reveive to transmit, e.g. by a Single Pole Double Throw switch. This can be seen in <imgref pic911> for the two situations "$A$ sends data to $B$" and "$B$ sends data to $A$". +Therefore, we have to switch on both sides from receive to transmit, e.g. by a Single Pole Double Throw switch. This can be seen in <imgref pic911> for the two situations "$A$ sends data to $B$" and "$B$ sends data to $A$". 
-Again, you can change the inputs $X0$ and $X1$ by clicking on the ''L'' and ''H'' nearby this labels. +Again, you can change the inputs $X0$ and $X1$ by clicking on the ''L'' and ''H'' nearby these labels. 
  
-The problem is, that in one time the output becomes an input, but boolean gates an algebra result everytime in boolean outputs.+The problem is, that at one time the output becomes an input, but boolean gates an algebra result every time in boolean outputs.
  
 <WRAP><well> <WRAP><well>
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 </well></WRAP> </well></WRAP>
  
-We still could try solve it with gates, as seen in <imgref pic912>: Each microcontroller has an enable signal (''EN0'', ''EN1''). Both outputs from the microcontrollers have to be combined with another gate in such a way, that the result shows the enabled signal. +We still could try to solve it with gates, as seen in <imgref pic912>: Each microcontroller has an enable signal (''EN0'', ''EN1''). Both outputs from the microcontrollers have to be combined with another gate in such a way, that the result shows the enabled signal. 
  
-The problem here: We are back to a two wire system. So, we need to "split up" the OR gate somehow..+The problem here: We are back to a two-wire system. So, we need to "split up" the OR gate somehow..
  
 <WRAP><well> <WRAP><well>
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 </well></WRAP> </well></WRAP>
  
-For this we can use the Tri-State gate: This enables to switch an output to high ohmic. This means this output does not provide any current anymore, so this output is not driven anymore.+For this we can use the Tri-State gate: This enables us to switch output to high ohmic. This means this output does not provide any current anymore, so this output is not driven anymore.
  
 <WRAP><well> <WRAP><well>
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 </callout> </callout>
  
-Since the timing diagram is of importance not only for the upcoming courses like Electronics (in the 3rd semester) I recommend to watch the following video sequence.+Since the timing diagram is of importance not only for the upcoming courses like Electronics (in the 3rd semester) I recommend watching the following video sequence.
  
 <WRAP> <WRAP>
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 </callout> </callout>
  
-Some of the circuits in the provious chapter looked suspiciously similar. We will now have a more deeper look onto this and try to convert some gates into each other.  +Some of the circuits in the previous chapter looked suspiciously similar. We will now have a deeper look into this and try to convert some gates into each other.  
-In this subchapter we will focus on combining NAND gates in order to build other gates. As we will see, based on the NAND and NOR gates any other gate and any other logic can be created.+In this subchapter, we will focus on combining NAND gates to build other gates. As we will see, based on the NAND and NOR gates any other gate and any other logic can be created.
  
 ==== 1.4.1 NAND in NOT ==== ==== 1.4.1 NAND in NOT ====
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 </well></WRAP> </well></WRAP>
  
-The conversion from NAND to NOT is relatively simple: When both inputs to NAND are the same (either '1' or '0') the output will be the negation of the input. This can also be seen in the truth table of the NAND gate: when the inputs as the same only the first and last row, have to be considered and lead to a inverting behaviour.+The conversion from NAND to NOT is relatively simple: When both inputs to NAND are the same (either '1' or '0') the output will be the negation of the input. This can also be seen in the truth table of the NAND gate: when the inputs as the same only the first and last rows, have to be considered and leading to an inverting behavior.
  
-A different approach to get an NOT is to set the second input to '1'. Here, the NOT can be 'deactivated' of with the second input. This can be tested in the <imgref pic34> by clicking on the input 'H' of the NAND gate on the right below.+A different approach to get a NOT is to set the second input to '1'. Here, the NOT can be 'deactivated' of with the second input. This can be tested in the <imgref pic34> by clicking on the input 'H' of the NAND gate on the right below.
  
 ==== 1.4.2 NAND in AND ==== ==== 1.4.2 NAND in AND ====
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 </well></WRAP> </well></WRAP>
  
-With the knwoledge from 'NAND to NOT' the NAND can be converted to AND: a negated NAND leads to an AND. It is roughly similar to 'not a no-go' is logically a 'go'.  +With the knowledge from 'NAND to NOT' the NAND can be converted to AND: a negated NAND leads to an AND. It is roughly similar to 'not a no-go' and is logically a 'go'.  
-Therefore, the NOT hat to be set behind the NAND.+Therefore, the NOT had to be set behind the NAND.
  
 ==== 1.4.3 NAND in OR ==== ==== 1.4.3 NAND in OR ====
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 </well></WRAP> </well></WRAP>
  
-When each input of a NAND gate is inverted the result acts like an OR gate. In order to understand this, one can again look onto the truth table of the NAND and the OR gate and try to invetigate what happens when the inputs of the NAND are negated. +When each input of a NAND gate is inverted the result acts like an OR gate. To understand this, one can again look at the truth table of the NAND and the OR gate and try to investigate what happens when the inputs of the NAND are negated. 
  
  
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 </callout> </callout>
  
-We have seen, that (at least) some of the gates can be represented by means of others. In order to approach this more systematically, we will now have a look onto the arithmetic rules of boolean algebra. These rules can be used to either build a logic cicruit out of the basis gates shown in chapter 1.2. On the other hand we are also able to simplify the logic circuits by ths rules.+We have seen, that (at least) some of the gates can be represented using others. To approach this more systematically, we will now have a look at the arithmetic rules of boolean algebra. These rules can be used to either build a logic circuit out of the basis gates shown in chapter 1.2. On the other hand, we are also able to simplify the logic circuits by these rules.
  
 ==== 1.5.1 The Set of Rules ==== ==== 1.5.1 The Set of Rules ====
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 It is possible to click on "math representation" and "algebraic representation" to switch both. It is possible to click on "math representation" and "algebraic representation" to switch both.
  
-Have a look for the algebraic representation. These are probably much simpler to remember!+Have a look at the algebraic representation. These are probably much simpler to remember!
  
 Be also aware, that the logical expressions sometimes are written as $X0$, $X1$, ... and sometimes with other letters, like $a$, $b$, ...  Be also aware, that the logical expressions sometimes are written as $X0$, $X1$, ... and sometimes with other letters, like $a$, $b$, ... 
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 |:::|$B \lor  B \rightarrow B                          $|:::    |  |:::|$B \lor  B \rightarrow B                          $|:::    | 
 |2  |**Duality**                                        | If $A$ is a statement of boolean algebra, so is $A^*$. \\ $A^*$ is obtained by exchanging $\land$ with $\lor$ and vice versa. |  |2  |**Duality**                                        | If $A$ is a statement of boolean algebra, so is $A^*$. \\ $A^*$ is obtained by exchanging $\land$ with $\lor$ and vice versa. | 
-|3  |**Neutral Element**                                | There exist a neutral element to the operators $\land$ and $\lor$. \\ Applying the oparator to a and the neutral element results in $a$. |+|3  |**Neutral Element**                                | There exist a neutral element to the operators $\land$ and $\lor$. \\ Applying the operator to a and the neutral element results in $a$. |
 |:::|$a \land 1 = a                                    $|:::    | |:::|$a \land 1 = a                                    $|:::    |
 |:::|$a \lor  0 = a                                    $|:::    |  |:::|$a \lor  0 = a                                    $|:::    | 
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 |:::|$a \land b = b \land a                            $|:::    |  |:::|$a \land b = b \land a                            $|:::    | 
 |:::|$a \lor  b = b \lor  a                            $|:::    |  |:::|$a \lor  b = b \lor  a                            $|:::    | 
-|7  |**Associative Law**                                | For the same operator bracketing can be moved. \\ associative means "to unite" or "to  connect" |+|7  |**Associative Law**                                | For the same operator bracketing can be moved. \\ associative means "to unite" or "to connect" |
 |:::|$a \land (b \land c) = (a \land b) \land c        $|:::    |  |:::|$a \land (b \land c) = (a \land b) \land c        $|:::    | 
 |:::|$a \lor  (b \lor  c) = (a \lor  b) \lor  c        $|:::    |  |:::|$a \lor  (b \lor  c) = (a \lor  b) \lor  c        $|:::    | 
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 |:::|$a \land (b \lor  c) = (a \land b) \lor  (a \land c)$|:::    |  |:::|$a \land (b \lor  c) = (a \land b) \lor  (a \land c)$|:::    | 
 |:::|$a \lor  (b \land c) = (a \lor  b) \land (a \lor  c)$|:::    |  |:::|$a \lor  (b \land c) = (a \lor  b) \land (a \lor  c)$|:::    | 
-|9  |**Law of Absorbtion**                                          | In bracketed formulas similar expressions can "absorb" each other. \\ This law can be drived from the laws (8), (5), (7)  |+|9  |**Law of Absorption**                                          | In bracketed formulas similar expressions can "absorb" each other. \\ This law can be derived from the laws (8), (5), (7)  |
 |:::|$a \land (a \lor  b) = a$ \\ $a \land (\bar{a} \lor  b) = a \land b $|:::    |  |:::|$a \land (a \lor  b) = a$ \\ $a \land (\bar{a} \lor  b) = a \land b $|:::    | 
 |:::|$a \lor  (a \land b) = a$ \\ $a \lor  (\bar{a} \land b) = a \lor  b $|:::    |  |:::|$a \lor  (a \land b) = a$ \\ $a \lor  (\bar{a} \land b) = a \lor  b $|:::    | 
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 |:::|$B +  B \rightarrow B                          $|:::    |  |:::|$B +  B \rightarrow B                          $|:::    | 
 |2  |**Duality**                                        | If $A$ is a statement of boolean algebra, so is $A^*$. \\ $A^*$ is obtained by exchanging $\cdot$ with $+$ and vice versa. |  |2  |**Duality**                                        | If $A$ is a statement of boolean algebra, so is $A^*$. \\ $A^*$ is obtained by exchanging $\cdot$ with $+$ and vice versa. | 
-|3  |**Neutral Element**                                | There exist a neutral element to the operators $\cdot$ and $+$. \\ Applying the oparator to a and the neutral element results in $a$. |+|3  |**Neutral Element**                                | There exist a neutral element to the operators $\cdot$ and $+$. \\ Applying the operator to a and the neutral element results in $a$. |
 |:::|$a \cdot 1 = a                                    $|:::    | |:::|$a \cdot 1 = a                                    $|:::    |
 |:::|$a +  0 = a                                    $|:::    |  |:::|$a +  0 = a                                    $|:::    | 
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 |:::|$a \cdot b = b \cdot a                            $|:::    |  |:::|$a \cdot b = b \cdot a                            $|:::    | 
 |:::|$a +  b = b +  a                            $|:::    |  |:::|$a +  b = b +  a                            $|:::    | 
-|7  |**Associative Law**                                | For the same operator bracketing can be moved. \\ associative means "to unite" or "to  connect" |+|7  |**Associative Law**                                | For the same operator bracketing can be moved. \\ associative means "to unite" or "to connect" |
 |:::|$a \cdot (b \cdot c) = (a \cdot b) \cdot c        $|:::    |  |:::|$a \cdot (b \cdot c) = (a \cdot b) \cdot c        $|:::    | 
 |:::|$a +  (b +  c) = (a +  b) +  c        $|:::    |  |:::|$a +  (b +  c) = (a +  b) +  c        $|:::    | 
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 |:::|$a \cdot (b +  c) = (a \cdot b) +  (a \cdot c)$|:::    |  |:::|$a \cdot (b +  c) = (a \cdot b) +  (a \cdot c)$|:::    | 
 |:::|$a +  (b \cdot c) = (a +  b) \cdot (a +  c)$|:::    |  |:::|$a +  (b \cdot c) = (a +  b) \cdot (a +  c)$|:::    | 
-|9  |**Law of Absorbtion**                                          | In bracketed formulas similar expressions can "absorb" each other. \\ This law can be drived from the laws (8), (5), (7)  |+|9  |**Law of Absorption**                                          | In bracketed formulas similar expressions can "absorb" each other. \\ This law can be derived from the laws (8), (5), (7)  |
 |:::|$a \cdot (a +  b) = a$ \\ $a \cdot (\bar{a} +  b) = a \cdot b $|:::    |  |:::|$a \cdot (a +  b) = a$ \\ $a \cdot (\bar{a} +  b) = a \cdot b $|:::    | 
 |:::|$a +  (a \cdot b) = a$ \\ $a +  (\bar{a} \cdot b) = a +  b $|:::    |  |:::|$a +  (a \cdot b) = a$ \\ $a +  (\bar{a} \cdot b) = a +  b $|:::    | 
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 </accordion> </accordion>
  
-The last 3 laws are probable a kind of unintuitive. Therefore, these are shown in other representations. in the following+The last 3 laws are probably kind of unintuitive. Therefore, these are shown in other representations. in the following
  
 ==== 1.5.2 Dive into Distributive Law  ==== ==== 1.5.2 Dive into Distributive Law  ====
  
-The distributive law can be shown on a simple example of daily life. \\+The distributive law can be shown as a simple example of daily life. \\
 When one says When one says
    "I'm happy with fries AND (a water OR a coke)"     "I'm happy with fries AND (a water OR a coke)" 
 he will be happy with he will be happy with
-   (fries AND a water) OR (fries AND a coke)+   (fries AND water) OR (fries AND a coke)
  
-Be aware, that the is no exclusiveness here. The person would also be happy with fries AND a water AND a coke!+Be aware, that the is no exclusiveness here. The person would also be happy with fries AND water AND a coke!
  
-The gate represenation is shown in <imgref pic37>. At the first glimpse, the output $Y$ of the upper circuit and the lower circuit look similar (they are indeed the same). +The gate representation is shown in <imgref pic37>. At first glimpse, the output $Y$ of the upper circuit and the lower circuit look similar (they are indeed the same). 
-Also the truth tables for the first gate ($Y'$, $Y''$, $Y'''$) and a larger truth table for all results is given. \\ +Also, the truth tables for the first gate ($Y'$, $Y''$, $Y'''$) and a larger truth table for all results are given. \\ 
-But the conversion of the upper one to the lower one is not intuitive here. That is why the multiple represenations and remembering the rules for boolean algebra is very important. Translating from one represenation into another one helps to use other tools in order to simplify systems!+But the conversion of the upper one to the lower one is not intuitive here. That is why the multiple representations and remembering the rules for boolean algebra are very important. Translating from one representation into another one helps to use other tools to simplify systems!
  
 <WRAP><well> <WRAP><well>
Zeile 596: Zeile 596:
  
  
-==== 1.5.3 Dive into Law of Absorbtion ====+==== 1.5.3 Dive into the Law of Absorption ====
  
-We will also try to transfer the law of absorbtion to a example of daily life. \\+We will also try to transfer the law of absorption to an example of daily life. \\
 When one says When one says
    "I'm happy with fries OR (fries AND a coke)"     "I'm happy with fries OR (fries AND a coke)" 
 he will be happy with he will be happy with
-   fries.. +   fries... 
 No matter whether there is coke with it.  No matter whether there is coke with it. 
  
-The absortion of the inverse ($a +  (\bar{a} \cdot b) = a +  b $) is also possible:\\+The absorption of the inverse ($a +  (\bar{a} \cdot b) = a +  b $) is also possible:\\
 When one says When one says
    "I'm happy with fries OR (no fries AND a coke)"     "I'm happy with fries OR (no fries AND a coke)" 
 he will be happy with he will be happy with
    fries OR a coke    fries OR a coke
-When he only gets fries the first part is true. When he only gets coke, the secont part is true. When he gets both, he of cource gets fries and therefore the firt part is true..+When he only gets fries the first part is true. When he only gets coke, the second part is true. When he gets both, he of course gets fries and therefore the first part is true...
  
-The gate represenation is shown in <imgref pic38>. When ignoring the blinking High and Low of the lines, also here the similarity of the upper and lower circuits may be not really intuitive.+The gate representation is shown in <imgref pic38>. When ignoring the blinking High and Low of the lines, also here the similarity of the upper and lower circuits may be not intuitive.
  
 <WRAP><well> <WRAP><well>
Zeile 623: Zeile 623:
 ==== 1.5.4 Dive into  DeMorgan's Rule ==== ==== 1.5.4 Dive into  DeMorgan's Rule ====
  
-At last, let's have a look onto DeMorgan's rule. The following instance shows it in daily life. \\+At last, let's have a look at DeMorgan's rule. The following instance shows it in daily life. \\
 When one says When one says
-   "I don't like fries AND i don't like coke" +   "I don't like fries AND I don't like coke" 
 he will be unhappy when he gets either fries, or coke, or (fries and coke). he will be unhappy when he gets either fries, or coke, or (fries and coke).
  
-The gate represenation is shown in <imgref pic39>. All four circuits show the same behaviour. \\ +The gate representation is shown in <imgref pic39>. All four circuits show the same behavior. \\ 
-On the left the NOT gate is explicitely shown. On the right the NOT gates are shrinked down to the circles either on the input or on the output. +On the left, the NOT gate is explicitly shown. On the right, the NOT gates are shrunk down to the circles either on the input or on the output. 
  
 <WRAP><well> <WRAP><well>
Zeile 640: Zeile 640:
   * any AND is substituted with OR plus   * any AND is substituted with OR plus
   * any OR is substituted with AND   * any OR is substituted with AND
-Important is, that also the most upper expression also have to be inverted.+Important is, that also most upper expressions have to be inverted.
  
 ==== 1.5.5 Example of a logic Simplification ==== ==== 1.5.5 Example of a logic Simplification ====
Zeile 653: Zeile 653:
  
 Based on the associative law, when purely AND gates or purely OR gates are stacked the inputs are interchangeable. \\ Based on the associative law, when purely AND gates or purely OR gates are stacked the inputs are interchangeable. \\
-Therefore, this stacking can be substituted with a gate symbol with multiple input. The two AND-gates shown in <imgref pic40> can be substituted with a single one. +Therefore, this stacking can be substituted with a gate symbol with multiple inputs. The two AND gates shown in <imgref pic40> can be substituted with a single one. 
  
-The essence auf the AND gate is: An AND gate - no matter how much inputs it has - will only output high, when all inputs are high. +The essence of the AND gate is: An AND gate - no matter how many inputs it has - will only output high when all inputs are high. 
  
 <WRAP><well> <WRAP><well>
Zeile 672: Zeile 672:
 ==== 1.6.2 Switchable Inverter ==== ==== 1.6.2 Switchable Inverter ====
  
-Sometimes it is important switch between inverting and not inverting an output. This can be done with the XOR gate. When the $EN$ in <imgref pic41> is active, the input $X$ will be inversed.+Sometimes it is important to switch between inverting and not inverting an output. This can be done with the XOR gate. When the $EN$ in <imgref pic41> is active, the input $X$ will be inversed.
  
 <WRAP><well> <WRAP><well>
Zeile 679: Zeile 679:
 </well></WRAP> </well></WRAP>
  
-One application for a switchable inverter would be an monochrome display, where every pixel can be set by one bit. When the display (or a small part like the cursor symbol) has to be inverted it would be great to do so with a simple gate. This can be seen in  +One application for a switchable inverter would be a monochrome display, where every pixel can be set by one bit. When the display (or a small part like the cursor symbol) has to be inverted it would be great to do so with a simple gate. This can be seen in  
 [[https://www.falstad.com/circuit/circuitjs.html?ctz=CQAgjCAMB0lwTAFkWRkBs8CsIDMMxd0AOI44ksATnXRHmJBy0iYFMBaMMAKDRy4MQNEB0SMRrRsR5hiVUWHStEueIrDrV6qfVxUeAJUXKQidIhMrx4erfjQcDnKxjEsfQqKqaQF0RSW-qy4IIyufnToAOy2EDGRUIqi8DwATsJ0uFjqImgRYJDp4ELZ6pqM+UmFxf5lfpZVrDUZang5eFpw1UUAMt6+-hw0rMG2AGYAhgA2AM5sTFA8-RzESuB0w6brEVNzCy7FW+3qx03gRRkcdR3Xjd3Nl0n1Kg8XR231HG3nNXKWq3WIg40WIlkkeFk7hS5EyJjhIVkQzIZmR8BUY1CrBcID28yWAHcUtEtENqKTLEUiRx4EgzMD4CT6XQqcT1DlGDSsHQOYTRNEOryQR1cGC+SCSEwhML2UJWSD0cz+ZLEJIeNSSSExQqVGrqSRKkMDXgxfLoiqjbDzJSkQDCpBGNhNiN6NznotdjN8UVjKt-NaAnl-BB1P5nPRHEkYB4lADAqi4+sAyEkji8Qt5SiA98VQ91aIs90-fdXPni2Yi-Hk2XjVhzYpIHS6yyy4Um-WuI3LE7xW3u27Ow7XS39VbLYxm0swFgAVVgfhwSy7Niy1VuKd0G71+LN3RgbvwL4+qIqm0OFhfG1PfsPa2qFpgeSE7378+uK-RTbqbTLJ+UnTVRHFI3T-LkeTlMs1jodZASiL9FFfQCrCVeVT1OKpiFLakFzhGlYTVNBQjEdZUABBhHSHFRogAfSUajIGogAPNZIDorB6OgMB6Oo+BaOgbBuMQGjcA4xt2IYgARABBAAVKSeAAIwbWFvg3C8-GnJYlLEM82jAUENNiIpGIbIcxAEdwIDELR6EsABZABLABjNIAHsnNcgA7AAXNzpmmNg0h4EzvlwKzEA3BRvgUbtLAkhzZgAB2mSYAE8AB1ZgJBzvIAC0yiS0gcgA3QLMt6VyAHNnOC7wqAUWkBCoML6CEWKQAAYVcgBXHzAtq1ZEBwVRNmiMazH0MxbM6nq+qCkLslCVRYjw4a0Cmukut67z+pCqhIEaKy1kqRpprstgAFtXLSVKBrGyxoiIkkFHrdq7O6xiBqQHBolYLh0Bepbpoky6PoGrBmFwWJogUGcVGmgBlXKHPGbzMrSNhqtmHb5o0VhoggVBGGiU66V6ABRCTMoAEwS5K0sygB6TLEocxi2GmTLJjSNI0oGzAiKEk9shAWJGkYABJAA5AA1cnDBkzL0vSzzMoACXl8meCAA| this more complex example]], where the display smiley can be inverted via the XOR gate during data transmission. The other logic component in this example will be explained in the following (sub)chapters. [[https://www.falstad.com/circuit/circuitjs.html?ctz=CQAgjCAMB0lwTAFkWRkBs8CsIDMMxd0AOI44ksATnXRHmJBy0iYFMBaMMAKDRy4MQNEB0SMRrRsR5hiVUWHStEueIrDrV6qfVxUeAJUXKQidIhMrx4erfjQcDnKxjEsfQqKqaQF0RSW-qy4IIyufnToAOy2EDGRUIqi8DwATsJ0uFjqImgRYJDp4ELZ6pqM+UmFxf5lfpZVrDUZang5eFpw1UUAMt6+-hw0rMG2AGYAhgA2AM5sTFA8-RzESuB0w6brEVNzCy7FW+3qx03gRRkcdR3Xjd3Nl0n1Kg8XR231HG3nNXKWq3WIg40WIlkkeFk7hS5EyJjhIVkQzIZmR8BUY1CrBcID28yWAHcUtEtENqKTLEUiRx4EgzMD4CT6XQqcT1DlGDSsHQOYTRNEOryQR1cGC+SCSEwhML2UJWSD0cz+ZLEJIeNSSSExQqVGrqSRKkMDXgxfLoiqjbDzJSkQDCpBGNhNiN6NznotdjN8UVjKt-NaAnl-BB1P5nPRHEkYB4lADAqi4+sAyEkji8Qt5SiA98VQ91aIs90-fdXPni2Yi-Hk2XjVhzYpIHS6yyy4Um-WuI3LE7xW3u27Ow7XS39VbLYxm0swFgAVVgfhwSy7Niy1VuKd0G71+LN3RgbvwL4+qIqm0OFhfG1PfsPa2qFpgeSE7378+uK-RTbqbTLJ+UnTVRHFI3T-LkeTlMs1jodZASiL9FFfQCrCVeVT1OKpiFLakFzhGlYTVNBQjEdZUABBhHSHFRogAfSUajIGogAPNZIDorB6OgMB6Oo+BaOgbBuMQGjcA4xt2IYgARABBAAVKSeAAIwbWFvg3C8-GnJYlLEM82jAUENNiIpGIbIcxAEdwIDELR6EsABZABLABjNIAHsnNcgA7AAXNzpmmNg0h4EzvlwKzEA3BRvgUbtLAkhzZgAB2mSYAE8AB1ZgJBzvIAC0yiS0gcgA3QLMt6VyAHNnOC7wqAUWkBCoML6CEWKQAAYVcgBXHzAtq1ZEBwVRNmiMazH0MxbM6nq+qCkLslCVRYjw4a0Cmukut67z+pCqhIEaKy1kqRpprstgAFtXLSVKBrGyxoiIkkFHrdq7O6xiBqQHBolYLh0Bepbpoky6PoGrBmFwWJogUGcVGmgBlXKHPGbzMrSNhqtmHb5o0VhoggVBGGiU66V6ABRCTMoAEwS5K0sygB6TLEocxi2GmTLJjSNI0oGzAiKEk9shAWJGkYABJAA5AA1cnDBkzL0vSzzMoACXl8meCAA| this more complex example]], where the display smiley can be inverted via the XOR gate during data transmission. The other logic component in this example will be explained in the following (sub)chapters.
  
-Another usage is the inversion of binary numbers in the arithmetic logical unit of the processor.+Another usage is the inversion of binary numbers in the arithmetic logic unit of the processor.
  
 ==== 1.6.3 Data Valve ==== ==== 1.6.3 Data Valve ====
Zeile 699: Zeile 699:
 ==== 1.6.4 Multiplexer and Demultiplexer ==== ==== 1.6.4 Multiplexer and Demultiplexer ====
  
-In the linked 'display example' in 1.6.2 there were a Multiplexer (MUX) and a Demultiplexer (DEMUX) visible. +In the linked 'display example' in 1.6.2 there was a Multiplexer (MUX) and a Demultiplexer (DEMUX) visible. 
  
-A **multiplexer** is a electronic switcher, which has several data inputs $D0$, $D1$ ... and one data output $Y$. Additionally to the data input there are also state inputs $S0$, $S1$, ... . The state inputs address which of the data input is routed to the data output. An example is given in <imgref pic43>. When $S0 = 0$ and $S1 = 0$ the zeroth data input $D0$ is the output, for $S0 = 1$ and $S0 = 0$ the first data input $D1$, for $S0 = 0$ and $S0 = 1$ the second. The 'inner live' of the multiplexer will be shown in the chapter 3.+A **multiplexer** is an electronic switcher, which has several data inputs $D0$, $D1$ ... and one data output $Y$. Additionally to the data input, there are also state inputs $S0$, $S1$, ... . The state inputs address which of the data input is routed to the data output. An example is given in <imgref pic43>. When $S0 = 0$ and $S1 = 0$ the zeroth data input $D0$ is the output, for $S0 = 1$ and $S0 = 0$ the first data input $D1$, for $S0 = 0$ and $S0 = 1$ the second. The 'inner life' of the multiplexer will be shown in chapter 3.
  
-A **demultiplexer** is the counterpart to the multiplexer: It has one data input $D$ and several data outputs $Y0$, $Y1$, ... . Again there are also state inputs $S0$, $S1$ ... . Here, the state inputs address to which data __output__ the single data input is routed. also this is shown in <imgref pic43>. +A **demultiplexer** is the counterpart to the multiplexer: It has one data input $D$ and several data outputs $Y0$, $Y1$, ... . Again there are also state inputs $S0$, $S1$ ... . Here, the state inputs address to which data __output__ the single data input is routed. Also, this is shown in <imgref pic43>. 
  
 <WRAP><well> <WRAP><well>
Zeile 710: Zeile 710:
 </well></WRAP> </well></WRAP>
  
-With the background given in subcapter 1.6.3 the demultiplexer can be derived. The example in the subchapter 1.6.3 an input were forwarded to 2 outputs. We will now have a look onto a demultiplexer with 4 outputs. For this instead of an AND gate with two inputs an AND gate with three inputs are used. The top-most input is the data input $D$ for all gates. The other two inputs address which of the AND gate will route the data input. When one has a detailed look onto the addressing inputs, one can see in any time that only one AND gate has both lower inputs high. +With the background given in subchapter 1.6.3, the demultiplexer can be derived. In the example, in subchapter 1.6.3 an input was forwarded to 2 outputs. We will now have a look at a demultiplexer with 4 outputs. For this instead of an AND gate with two inputs an AND gate with three inputs is used. The topmost input is the data input $D$ for all gates. The other two inputs address which of the AND gate will route the data input. When one has a detailed look at the addressing inputs, one can see at any time that only one AND gate has both lower inputs high. 
  
 <WRAP><well> <WRAP><well>
Zeile 725: Zeile 725:
  
   * A nice overview of core ideas for [[https://informatik.mygymer.ch/ef2019/rechnen-mit-strom|calculating with electricity]] has been compiled by Gymnasium Kirchenfeld (CH, in German)   * A nice overview of core ideas for [[https://informatik.mygymer.ch/ef2019/rechnen-mit-strom|calculating with electricity]] has been compiled by Gymnasium Kirchenfeld (CH, in German)
-  * Explanation of [[https://ca.wikipedia.org/wiki/CMOS|CMOS]] in the english Wikipedia+  * Explanation of [[https://ca.wikipedia.org/wiki/CMOS|CMOS]] in the English Wikipedia
   * Wiki page on [[https://en.wikipedia.org/wiki/Integrated_circuit|integrated circuits]]   * Wiki page on [[https://en.wikipedia.org/wiki/Integrated_circuit|integrated circuits]]
  
Zeile 781: Zeile 781:
 <panel type="info" title="Exercise 1.6.4. NAND-based gates"> <WRAP group><WRAP column 2%>{{fa>pencil?32}}</WRAP><WRAP column 92%> <panel type="info" title="Exercise 1.6.4. NAND-based gates"> <WRAP group><WRAP column 2%>{{fa>pencil?32}}</WRAP><WRAP column 92%>
  
-Realize the logic functions of NOT, AND, OR, NOR, XOR and XNOR exclusively with NAND gates.+Realize the logic functions of NOT, AND, OR, NOR, XOR, and XNOR exclusively with NAND gates.
  
  
Zeile 789: Zeile 789:
  
 An inverter can be realized with a NAND gate when both inputs are connected to the same input. \\ An inverter can be realized with a NAND gate when both inputs are connected to the same input. \\
-When the input is $1$ the output will be $0$ and vise versa.+When the input is $1$ the output will be $0$ and vice versa.
  
 <WRAP> <WRAP>
Zeile 819: Zeile 819:
 **__NOR__** **__NOR__**
  
-Again the NOR gate can be derived from the NOT gate an OR gate.+Again the NOR gate can be derived from the NOT gate and OR gate.
  
 <WRAP> <WRAP>
Zeile 834: Zeile 834:
     - The ladder one is $X0\cdot X1$, which is only $1$ for both inputs as $1$. \\     - The ladder one is $X0\cdot X1$, which is only $1$ for both inputs as $1$. \\
     - For detecting $X0=0\; and\; X1=0$ one can use $\overline{X0+X1}$, which is only $1$ for both inputs are $0$.      - For detecting $X0=0\; and\; X1=0$ one can use $\overline{X0+X1}$, which is only $1$ for both inputs are $0$. 
-  - This two gates have to be combined in such a way that, only for $(X0=0, X1=0)$, $(X0=1, X1=1)$ the final output is $1$. \\ In other words: only when the output of the AND- and the NOR-gates is $0$, the final output has to be $1$. \\For this a NOR gate can be used. +  - These two gates have to be combined in such a way that, only for $(X0=0, X1=0)$, $(X0=1, X1=1)$ the final output is $1$. \\ In other words: only when the output of the AND- and the NOR-gates is $0$, the final output has to be $1$. \\For this, a NOR gate can be used. 
-  - All of the mentioned gates can be build based on NAND gates. This is shown in <imgref Ex_1_6_4_5 >.+  - All of the mentioned gates can be built based on NAND gates. This is shown in <imgref Ex_1_6_4_5 >.
  
 <WRAP> <WRAP>
Zeile 845: Zeile 845:
 The shown circuit can even be simplified:  The shown circuit can even be simplified: 
   * Two Not-gates in series can be skipped since $\overline{\overline{X}}=X$. \\ With this knowledge, the XOR-gate needs 6 NAND gates.   * Two Not-gates in series can be skipped since $\overline{\overline{X}}=X$. \\ With this knowledge, the XOR-gate needs 6 NAND gates.
-  * An alternative setup for the XOR-gate can be build by one NAND-, one OR- and one AND-gate. This circuitry needs also 6 NAND gates. \\The cicuitry is not shown.+  * An alternative setup for the XOR-gate can be built by one NAND-, one OR-, and one AND-gate. This circuitry needs also 6 NAND gates. \\The circuitry is not shown.
   * The circuity with the least NAND gates is shown in <imgref Ex_1_6_4_6 >   * The circuity with the least NAND gates is shown in <imgref Ex_1_6_4_6 >
  
Zeile 862: Zeile 862:
 <panel type="info" title="Exercise 1.6.5. NOR-based gates"> <WRAP group><WRAP column 2%>{{fa>pencil?32}}</WRAP><WRAP column 92%> <panel type="info" title="Exercise 1.6.5. NOR-based gates"> <WRAP group><WRAP column 2%>{{fa>pencil?32}}</WRAP><WRAP column 92%>
  
-Realize the logic functions of NOT, OR, AND, NAND, XOR and XNOR exclusively with NOR gates.+Realize the logic functions of NOT, OR, AND, NAND, XOR, and XNOR exclusively with NOR gates.
 </WRAP></WRAP></panel> </WRAP></WRAP></panel>
  
Zeile 878: Zeile 878:
 <button size="xs" type="link" collapse="Solution_1_6_6_1_Solution_path">{{icon>eye}} Solution for 1. </button><collapse id="Solution_1_6_6_1_Solution_path" collapsed="true"> <button size="xs" type="link" collapse="Solution_1_6_6_1_Solution_path">{{icon>eye}} Solution for 1. </button><collapse id="Solution_1_6_6_1_Solution_path" collapsed="true">
  
-Often the formula can be easier analysed with in the more compact terminology. \\ +Often the formula can be easier analyzed with more compact terminology. \\ 
-Additionally the brackets can be ignored in the case of products - similar to the convention in math for $(a \cdot b) + (c \cdot d) = ab + cd$+Additionally, the brackets can be ignored in the case of products - similar to the convention in math for $(a \cdot b) + (c \cdot d) = ab + cd$
  
 $Y = \color{blue}{\overline{X_0}}\;\color{green}{\overline{X_1}}\;\color{red}{\overline{X_2}}$$ +  \color{cornflowerblue}{X_0 }\;\color{yellowgreen}{   {X_1}}\;\color{red}{\overline{X_2}}$$ +  \color{blue}{\overline{X_0}}\;\color{green}{\overline{X_1}}\;\color{salmon}{      {X_2}}$$ +  \color{cornflowerblue}{X_0 }\;\color{yellowgreen}{   {X_1}}\;\color{salmon}{      {X_2}}$ $Y = \color{blue}{\overline{X_0}}\;\color{green}{\overline{X_1}}\;\color{red}{\overline{X_2}}$$ +  \color{cornflowerblue}{X_0 }\;\color{yellowgreen}{   {X_1}}\;\color{red}{\overline{X_2}}$$ +  \color{blue}{\overline{X_0}}\;\color{green}{\overline{X_1}}\;\color{salmon}{      {X_2}}$$ +  \color{cornflowerblue}{X_0 }\;\color{yellowgreen}{   {X_1}}\;\color{salmon}{      {X_2}}$
Zeile 919: Zeile 919:
 <button size="xs" type="link" collapse="Solution_1_6_6_3_Solution_path">{{icon>eye}} Solution for 3. </button><collapse id="Solution_1_6_6_3_Solution_path" collapsed="true"> <button size="xs" type="link" collapse="Solution_1_6_6_3_Solution_path">{{icon>eye}} Solution for 3. </button><collapse id="Solution_1_6_6_3_Solution_path" collapsed="true">
  
-Again, the formula can be easier analysed with in the more compact terminology. \\ +Again, the formula can be easier analyzed with more compact terminology. \\ 
-Additionally the brackets can be ignored in the case of products - similar to the convention in math for $(a \cdot b) + (c \cdot d) = ab + cd$+Additionally, the brackets can be ignored in the case of products - similar to the convention in math for $(a \cdot b) + (c \cdot d) = ab + cd$
 \begin{align*} \begin{align*}
 Y &= \color{cornflowerblue}{X_0 }\;\color{yellowgreen}{   {X_1}}\;\color{salmon}{      {X_2}}\;\color{brown}{\overline{X_3}}  Y &= \color{cornflowerblue}{X_0 }\;\color{yellowgreen}{   {X_1}}\;\color{salmon}{      {X_2}}\;\color{brown}{\overline{X_3}} 
Zeile 1000: Zeile 1000:
 \end{align*} \end{align*}
  
-Generally, the first step would be to see which of the parts show already a NAND configuration. In the following these are marked in $\color{magenta}{magenta}$.\\ +Generally, the first step would be to see which of the parts show already a NAND configuration. In the following, these are marked in $\color{magenta}{magenta}$.\\ 
-In this case there are no terms with NAND available.+In this case, there are no terms with NAND available.
  
-One of next steps is to do substitutions with DeMorgans rule: $\overline{a+b}=\overline{a}\cdot\overline{b}$. \\+One of the next steps is to do substitutions with the DeMorgans rule: $\overline{a+b}=\overline{a}\cdot\overline{b}$. \\
 This can be used on the outer negation: This can be used on the outer negation:
  
Zeile 1033: Zeile 1033:
 </WRAP></WRAP></panel> </WRAP></WRAP></panel>
  
-<panel type="info" title="Exercise 1.6.8. step by step example for logic simplification using boolean rules"> <WRAP group><WRAP column 2%>{{fa>pencil?32}}</WRAP><WRAP column 92%>+<panel type="info" title="Exercise 1.6.8. step-by-step example for logic simplification using boolean rules"> <WRAP group><WRAP column 2%>{{fa>pencil?32}}</WRAP><WRAP column 92%>
  
 Hints for the clip:  Hints for the clip: 
   * The ladder logic is not necessary for our course.   * The ladder logic is not necessary for our course.
-  * Example 1 ist quiet exhausting including a recap of the boolean rules $\rightarrow$ you can skip this example+  * Example 1 is quite exhausting including a recap of the boolean rules $\rightarrow$ you can skip this example
   * Example 2 starts at 17:17   * Example 2 starts at 17:17
   * Example 3 starts at 21:00   * Example 3 starts at 21:00
   * Example 4 starts at 28:27   * Example 4 starts at 28:27
-  * Example 5-8 start at 32:33+  * Examples 5-8 start at 32:33
  
 {{youtube>59BbncMjL8I}} {{youtube>59BbncMjL8I}}
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 <panel type="info" title="Exercise 1.6.9. XOR in Cryptography"> <WRAP group><WRAP column 2%>{{fa>pencil?32}}</WRAP><WRAP column 92%> <panel type="info" title="Exercise 1.6.9. XOR in Cryptography"> <WRAP group><WRAP column 2%>{{fa>pencil?32}}</WRAP><WRAP column 92%>
  
-In the following EXCEL file an example of symmetric encryption can be found: {{introduction_to_digital_systems:xor_in_cryptography.xlsx}}+In the following EXCEL file, an example of symmetric encryption can be found: {{introduction_to_digital_systems:xor_in_cryptography.xlsx}}
  
   * Try to understand {{wp>XOR_cipher}} with this example.   * Try to understand {{wp>XOR_cipher}} with this example.