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introduction_to_digital_systems:realization_of_comb._logic [2021/10/18 02:13]
tfischer |
introduction_to_digital_systems:realization_of_comb._logic [2022/06/28 02:00]
tfischer |
| ====== Realization of Combinatorical Logic ====== | ====== 4. Realization of Combinatorical Logic ====== |
| | |
| | ===== 4.1 Preparation ===== |
| |
| In the last chapter we investigated the Therm-o-Safety example. From this, it was possible to create the logic formula via sum of products of products of sums (see <imgref pic01>). | In the last chapter we investigated the Therm-o-Safety example. From this, it was possible to create the logic formula via sum of products of products of sums (see <imgref pic01>). |
| The main question is now: which generalization of the shown logic can be found? | The main question is now: which generalization of the shown logic can be found? |
| |
| ===== History of the Logic Families ===== | ==== 4.1.1 History of the Logic Families ==== |
| |
| A huge variety of integrated circuits (ICs) were used historically. <imgref pic03> shows two separate integrated circuits: There can be single or multiple gates in an IC with two or more inputs. The most used IC series was the 74xx ICs, where the xx are numbers which define the internal logic. | A huge variety of integrated circuits (ICs) were used historically. <imgref pic03> shows two separate integrated circuits: There can be single or multiple gates in an IC with two or more inputs. The most used IC series was the 74xx ICs, where the xx are numbers which define the internal logic. |
| </WRAP> | </WRAP> |
| |
| ===== Logic Stages===== | ==== 4.1.2 Logic Stages==== |
| |
| From the <img pic02> we know how the logic for the sum of products looks like. in <imgref pic05> also the gate logic for the product of sums is shown. | From the <img pic02> we know how the logic for the sum of products looks like. in <imgref pic05> also the gate logic for the product of sums is shown. |
| </WRAP> | </WRAP> |
| |
| Often a simplification of the circuit represenation is used. There the multiple input ant output lines are reduced to one single line, representing a bus (= multiple parallel lines). | Often a simplification of the circuit represenation is used. There the multiple input and output lines are reduced to one single line, representing a bus (= multiple parallel lines). |
| Only the inputs which where the crossing of the lines are marked with a black dot are used as an input for the stages. These nodes are programmable and are usually set during production. | Only the inputs which where the crossing of the lines are marked with a black dot are used as an input for the stages. These connections are fixed. Often also programmable connections are used, wich are usually set during production. |
| The logic stages can be seen in <imgref pic06>. | The logic stages can be seen in <imgref pic06>. |
| |
| </WRAP> | </WRAP> |
| |
| | ===== 4.2 Programmable Logic Device ===== |
| | |
| | |
| | When there are programmable connections, the IC is called programmable logic device (PLD). Depending on the position of the programmable connections, these PLDs are separated into (see <imgref pic07>): |
| | - Programmable Array Logic (PAL): first stage is programmable, second stage is fixed |
| | - Programmable Logic Element (PLE): first stage is fixed, second stage is programmable |
| | - Programmable Logic Array (PLA): both stages are programmable |
| | |
| | |
| | <WRAP center> |
| | <imgcaption pic07| different types of PLDs> |
| | </imgcaption> |
| | {{drawio>plds}} |
| | </WRAP> |
| | |
| | |
| | ===== 4.2.1 Programmable Logic Elements ===== |
| | |
| | PLEs have fixed AND array logic in stage 1. This is often used in memory chips. \\ |
| | The AND array logic for memory chips represents a list of increasing digital values (see left stage in <imgref pic08>). |
| | In the picture the first 6 rpime numbers are stored in a 4-bit addressed 4-bit memory. |
| | The input value ''0100'' activates only one AND-gate, which enables one column of the OR array logic to be output. |
| | |
| | <WRAP center> |
| | <imgcaption pic08| PLE as memory device> |
| | </imgcaption> |
| | {{drawio>ple}} |
| | </WRAP> |
| | |
| | In <imgref pic10> the simulation shows a PLE. in the top left corner the address is shown in decimal. The logic enables only the address ''0'' up to ''8'' to have an output. The address increases and therefore step by step the information - given by the right-side array - is read. On the bottom right corner the memory of the address is shown in decimal. By clicking on the switches of the right-side, second stage one can also reprogram the stored information. |
| | |
| | <wrap #SimulationPLE /> |
| <WRAP><well> | <WRAP><well> |
| <imgcaption pic0x|Simulation of an Inverter></imgcaption> \\ | <imgcaption pic10|Simulation of a PLE></imgcaption> \\ |
| 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E5E6c0FdrGjhpSwQjdrrjYiHYQB-CWwUYsh1iyh5r-r4QRTd0-AysIbMgU9djo00Qm1wLdiOCUobSPNelgtvo8LnMlSkaPSoazYqzOxZss8jD9Tls-BOr0adiGdfAJDTQnpRQHIgwyBDJfwFEyBWbgl2bxw9NmaiAtM2aSB+bH19ghbTRebRatxxbMAWSPIgkRiCBcZOaOBCh1BFbcAhwVaxa3J1gWTO0paRj6BZb9aNbagExtb1BTbbwAAlZIJwJmf8K2CwGY8AaACuU8A8UyTABAEIbGHITgB2tICIRsL4F2x6N2lUVeT2q0b2tdJQf2wO1UEOyKODZ2+I6xaOt2sAOOigfMH2pOgOiAIOkOrYQ9TOs8d2mOj2r2wuxOv2kuyoTgK0T8NjQkOI2QJ7YgT6oipPHCjMhawGssWMubDMro-6ksbMMe1SuanE-6zMGe8at6Oa+NcGvutgC7RsB4+PasTwhMC7N4B432asJessLen4WwP0vuYsTei7JmLeysQyZsVuxxS+1BXiQkJmL0fExGc0E4HuWZEAXQAAOQAAUABVAAFRNA-htvNFMhttxi+AAHkYGoHYG4Z7i20EBxgjabIgA noborder}} |
| </well></WRAP> | </well></WRAP> |
| |
| | There are different types of memory available. The <imgref pic09> shows an overview separated by the different physically concepts of writing and clearing the information. |
| | |
| | A good practical example for an application are key cards or canteen cards (like your mensa card). There a small Operating system is stored in a ROM. They also use a one time programmable (OTP) PROM in order to secure the internal cryptographic secret. In a Flash-ROM the user can write additional reprogrmmable data. |
| | |
| | <WRAP center> |
| | <imgcaption pic09| comparison of the different memory types> |
| | </imgcaption> |
| | {{drawio>memorytypes}} |
| | </WRAP> |
| | |
| | ===== 4.2.2 Programmable Logic Arrays and Programmable Logic Elements ===== |
| | |
| | PLA were often used as glue logic, but are nowaday rarely in use. <imgref pic11> shows the principal setup. |
| | Based on PLAs - and in in special on PLEs - more complex logic devices are developed. |
| | |
| | <WRAP><well> |
| | <imgcaption pic11|Simulation of a PAL></imgcaption> \\ |
| | {{url>https://www.falstad.com/circuit/circuitjs.html?hideSidebar=true&ctz=CQAgzCAMB0lwrFWAOZAmALATgGxcmvMhvFvIvJCIhhPAKYC0AjMwFDOXU4jNpXIqfIdSjUO8NCH5V4OZNLggcS5uDHw2ASRALmPBRirHoFNgBldVhYwVSqAMwCGAGwDO9UZDYB3EI0xrK28-BTDeHhDdIX5FGONfOOpJJOEoRJleWMzUdL9M5iwpTLkFKJKVJLQcDDz-AHYpG0aIupZIWuam9MtGFq7-O14QZ3dPRG8dPql9BqkjMRgzKbQwGZ4AtZAFkzNe1e7NqVtpMVGPL0SAmqtrzrKr6s7-A+DHrZtX2aij7apf3LeSysJpCPjKWozEauC4TK76PQdP68JE-Tjzf7o3QPPwsFI2LHfeHEW5YnH+ZgkglUh69MkUlInKHncbpKaEjZYnZIMy43LMJEYRG1bwAZReQpRtQCksBZxhnioYDY4pY8ilFPVcqkLLEytxmDC-0N2LaCOimrC5NsRsGVvSqv5SJtppEuqV8KRBK91paC2mrqutpOgJVgw1IbKw3d4EezxlgdCyPtUTkEeFdTTIO2enBUUl2YLqMSCwFtVLsXz8W4WQSfizaAUWz45ObjfAM2LfmbzpNZfS-HqEuDmCoN1q7EHlotarH5d4bCnLsEgzn2wXS9ta4ni8gQ5OWKEYB4O83ekZK+Yx-Xk7306xs9419Pd5l5+Oo6fJ4X3Zm9Q2fb-nUWyZM2QGpjwoHFEoVa8EUNaFPYJZCEBpbwfmegkgW4GJFmWGYSKuE8MwQEHjhSa5HolQ-IEuQJvoCSOrwpFUcYpwxvq4YPqxbT9AMDFmj6FJIgJYp2sxGz8tR8pjHqQbvuJonwuqD7mkpBoFoyfbUWGap6KRanSTqCpyaqgEAQW0lqBx8kSTmdlojSFIkupDJNASKSuXpdmluRLwfJ8zY6QaNx0U8ER1haiGpOhEiyMR8GXvBagTOInDxdIoVUOFKUaIkK7hZk4U0TcAl3NIWw0UFxogZVyl2JKCwmminmVHixR1bilITm13UVUhfINYYQ0OsO0iSm+-WLNCskeqq5omt5rxsTZGl2IEk3LfV0gbQtnXiWgG25FtjojS6y3sSZHpdSJvVIltuItGVLQPeGh3SnYdVMYtn32DJFzXRKEVA69PG-ZmkETSNEHSGmkqEJEJZ2HD0PIeNhjZTcsHhWmxVEdILQgS0URE1IIGSiTxQTSazW7vuNMbZ+-CGBur4LbtlTMzedMHUd2WQCzt77utIqKILPMnCQkTbAsL7C4Yaa2FQGCy6z+7mlLmrK6rQtjZrMra8rP4djmxqNSulPUEiWxCpFaaULUWwO3Usu4DW2CI34ssrq7nv2UKw2mxDOaBwHwe2+GEdRE2iXbFjcbgPBCYYPHTER5LWPRldsZ8tsiuGPHj1k0nfqF8JjtJ-2KeEadQcutX02reJ+u5A3aLqvrGtl5N+smm3ukayu3lt-9iqxmZ5tmwXovWdnnH1z7w2RSwJJgJXWHd1ia-HFym8dz7ysW+8xcfjb3fhdvLzjmXPtu2gfpu946Xu27t-EaIZjP3DtHK4EuWyPlX+kI-SBBKo7WI5VL5VTJhA14UDtpGAxn8a0W8IFb1il1VeaDV4YObgLf2+CxI93wZNKBl1Zrj2nIg6cZDZ4UPniaMAJJSG4O8kw6U5p4GDXAMw3I8Da7UJdGQ4y9DPTgMxNbVhhMIGE1YU2XhickJpxITHP6jg54JzWGbRRdQmyxFUeHFRyDw6zEakSL2hhTEY3JLLfBstQFowwIEb+hF6wni2DbfaniYHGMtoIvuhCJaMOYZ+Y84slycOYQJMJ3Mzw8I+kqDuatwzsL1Ek3WJwwB5mkG7OW4ksnHAKrk5JbDwSPjQMUjJjCylM0qYkDx15SHXktseJUZNmn41aSbLpsEwApDTH0gayIwDPiVCkDC4AVb2RGX7AZUzJRgCmTDGZKSOlJleHo5egRXgJi0aNTJjTNmNw0bnApKTKxXBelsAMey0T3Wuf2W5uk+GHKOdlGaAMc75LKXwi5XV1RnLYX8sagLGEXPmgCxpnDKyj1MiCxpYK2J0M+fPF5J4mxrOcpCB5WDl5Yh2agvFkKTxKkxb8HZcDgXlQpTcJ5oQxnFEJuMuKNZBkWjZf-cQbheDgjJApFaCpEjZkJOCI+U5syXliOOY2WZnx6ExQWOVvBmUWOVe5NVLsRamnepqsW9kdUwy5vDQJfhsw6uFcy7lZraJaoFWMNgVrwQVIMHYR+o8hVOrdta1xNZGyH2kEfVVfr9WPyRjkl14b0iOrJk5VJdqPAepjROT1syeAxIWeqCZ6b5E+oWbGkk3ho15wjZreN9BE3Fp5Um8O3sZaRUarW0tYbNatzTIWqt1B2y5EkFGdR9rTXgh7R2ptbjqDgklPAPMYbJ3zAUEOiZQ7u3tnKEoOQ-M53BT1WurdmahXwVKHBKQ5AhnRWPUkM95QbhnvvkelVmVagHpxne4N26X27vyC0V9K5t3lE-ZzB+fsb3bG2X+8kQHr1MqQvi0DBMpAqBEHQcQH6yYpCA6GfISh4NJBwOY2DyglBAZw4jAAsth2YmQcAgWkKYNgpHCPkZaJR4o1HNAAA8r5CBIasXMahOhUGgGwdjK9OMeR4+uFcAmhNYCwCiZoQ5WC8YtJJikMmBRNh5YpiTgnnK8B9rpiAfGQDKcYFgTC-wgKUgM0p7TLB6iqaHpweTyArNaaE4QezNUnMuf4zZ9zsNT5DkIDQazQmSIycIDveAgXyDiZ81J5GxwgJBdi0ZmzlJ-PrmS4Z4z1QlT+m45M7zqXQsrkWZiIghWUvGek5M8zQ5FlFeM4UWr6gGtVd8zh7YNS15deC655yvGymcBkxgTg7XQtKFG4lyxfW4svGVk63r42XikBzNKVYQ4hSbZCxSOza2GSbeQNt-rJnhrSlQkd5bK99vlku9l7TlJVPbNYFkY7c3HtwUgi9woI2dsfeqHYF799NNzdy1bbK6AraNe02DpxdhIe0BB8VzKYzIKQ76b9rTIVyw3HKvAMlrwG6-Hx37dqccOH9LJX1InfUSeCRxxwpEdOfil3O0egnDOgbM-yuTqw3OIlegpD89cAANDJfUCRJxZiLtAQT4zXOl94Jc4VPgtEliAEXypxVASIxEBQTH1wAE1dYml15+A3tRDdRBIjwM3mHcOm4Y3Bokbn+k4A-KN7gwWFg5f6UPTAKVnPrh975lIuuZRqBw79kPruj2mYlJHyAimY+7dkDVvEMmVDzGRE1+oY4SIMkz7Ecsc3bOyGQGoDP1AsI57S3n7gEAq9yG-Cnvo3Bs9yG96XocRAjZECs63ocuvahR+D936g8eR9J7H8j2wMnSDNH19Pkvs-kCZ9mH0fXzWV-GbX9X8zc6g875s3vuQ02vcz+U2sI99RHYjOoPUbbKe2tRcdvAB9j-L-adSa-xOFBP-H7sbHh0C37gCgFRZP5zZ9KGCBDHgjb3xf5AF7ZOIVy-yQHI4jIwGOzYDAboFX4F4oEdgwF4Hf4xaHRqDHiQSBCAFgFUEUGXY6o0EjKIDkGTJUHzjP7MCQhoAUGEA7QcFzbu4T4yb1AQBZ6IHKDO5DiiGSFGwp5CFEBqAyFEACHI4KGUYgDKE4At4+YABGLw3aVBygYACQ+hnAI+Bmq6fB3g7G4yWQjsmWtQWgAAcgAAoACqAAKt-pAIgBbpAGIX0o4SAAAPJeEeHeFAA noborder}} |
| | </well></WRAP> |
| | |
| | Nowadays High Capacity Programmable Logic Devices are in use: |
| | * These are either **Complex Programmable Logic Devices** (CPLD), which have multiple sum of products or products of sum stages, with small storages in between. |
| | * There are also **Field-Programmable Gate Arrays** (FPGA). These have a huge number (>100'000) of simple functional blocks. One functional block contains the logic gate circuit and storage elements. Between the blocks are broad binary busses. The logic circuits, storage elements and bus allocation can be changed by reconfiguration. In <imgref pic12> the logic gate circuit is represented by a truth table. The storage element called flipflop will be investigated in the naex chapter. |
| | |
| | FPGAs can be used in order to test new microcontroller and microchips. For this the FPGA is configurated in such a way, that it resembles the new chip. |
| | |
| | <WRAP center> |
| | <imgcaption pic12| CPLD> |
| | </imgcaption> |
| | {{drawio>cpld}} |
| | </WRAP> |
| | |
| | <WRAP> |
| | A deeper explanation of the FPGA can be found here: |
| | {{youtube>lLg1AgA2Xoo}} |
| | </WRAP> |
| |
| ~~PAGEBREAK~~ ~~CLEARFIX~~ | ~~PAGEBREAK~~ ~~CLEARFIX~~ |