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introduction_to_digital_systems:realization_of_comb._logic [2022/06/28 01:54]
tfischer 		introduction_to_digital_systems:realization_of_comb._logic [2022/06/28 02:00]
tfischer
Zeile 101: Zeile 101:
 In <imgref pic10> the simulation shows a PLE. in the top left corner the address is shown in decimal. The logic enables only the address ''0'' up to ''8'' to have an output. The address increases and therefore step by step the information - given by the right-side array - is read. On the bottom right corner the memory of the address is shown in decimal. By clicking on the switches of the right-side, second stage one can also reprogram the stored information. In <imgref pic10> the simulation shows a PLE. in the top left corner the address is shown in decimal. The logic enables only the address ''0'' up to ''8'' to have an output. The address increases and therefore step by step the information - given by the right-side array - is read. On the bottom right corner the memory of the address is shown in decimal. By clicking on the switches of the right-side, second stage one can also reprogram the stored information.
  
 +<wrap #SimulationPLE />
 <WRAP><well> <WRAP><well>
 <imgcaption pic10|Simulation of a PLE></imgcaption> \\ <imgcaption pic10|Simulation of a PLE></imgcaption> \\