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introduction_to_digital_systems:sequential_logic [2023/02/04 12:44]
mexleadmin [Bearbeiten - Panel] 		introduction_to_digital_systems:sequential_logic [2023/03/27 11:52]
mexleadmin
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 The most important term for the upcoming topics is the word **state**. But what is a state? \\ It is a unique situation, where the possible next steps (= possible next states), the inner behavior or the outputs are distinguishable from other situations. The most important term for the upcoming topics is the word **state**. But what is a state? \\ It is a unique situation, where the possible next steps (= possible next states), the inner behavior or the outputs are distinguishable from other situations.
-Here some practical examples:+Here are some practical examples:
   * Being happy or being sad, are two different states, since the inner behavior is different (this least often also to a different output).    * Being happy or being sad, are two different states, since the inner behavior is different (this least often also to a different output). 
-  * Similarly, an empty memory (or harddrive) is in a different state compared to a filled one.  +  * Similarly, an empty memory (or hard drive) is in a different state compared to a filled one.  
-  * A traffic light showing green has a output distinguishable from red, or yellow. +  * A traffic light showing green has an output distinguishable from red, or yellow. 
-Sequential logic is used to describe logic cicruits which show internal states ("stateful logic"), and therefore have at least one memory element (= flip-flop). +Sequential logic is used to describe logic circuits that show internal states ("stateful logic"), and therefore have at least one memory element (= flip-flop). 
  
 The following terminology is used in the upcoming explanations: The following terminology is used in the upcoming explanations:
-  * The **input vector** $\vec{X}$ represents the $k$ inputs $X_0 ... X_{k-1}$ +  * The **input vector** $\vec{X}$ represents the $k$ inputs $X_0 ... X_{k-1}$. 
-  * The **output vector** $\vec{Y}$ represents the $l$ outputs $Y_0 ... Y_{l-1}$ +  * The **output vector** $\vec{Y}$ represents the $l$ outputs $Y_0 ... Y_{l-1}$. 
-  * The **state vector** $\vec{Z}$ represents the $m$ inputs $Z_0 ... Z_{m-1}$ +  * The **state vector** $\vec{Z}$ represents the $m$ inputs $Z_0 ... Z_{m-1}$. 
-  * The sign $(n)$ or $n$ marking the current point in time and therefore e.g. the current state $Z_0(n)$ +  * The sign $(n)$ or $n$ marking the current point in time and therefore e.g. the current state $Z_0(n)$. 
-  * The sign $(n+1)$ or $n+1$ marking the next upcomming point in time and therefore e.g. the next state $Z_0(n+1)$ +  * The sign $(n+1)$ or $n+1$ marking the next upcoming point in time and therefore e.g. the next state $Z_0(n+1)$. 
-  * Sequential logic circuits are also called **Finite State Machines** (FSM) or sometimes also shortened to "state machine"+  * Sequential logic circuits are also called **Finite State Machines** (FSM) or sometimes also shortened to "state machines".
  
 The <imgref pic04> shows the different terms in an abstract diagram. The "current" output values are here the values, which are shown after the delay time of the gates (about some nanoseconds). The <imgref pic04> shows the different terms in an abstract diagram. The "current" output values are here the values, which are shown after the delay time of the gates (about some nanoseconds).
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 <WRAP> <imgcaption pic06| Abstract View onto a Sequential Logic> </imgcaption> {{drawio>ViewOnSequentialLogic1.svg}} </WRAP> <WRAP> <imgcaption pic06| Abstract View onto a Sequential Logic> </imgcaption> {{drawio>ViewOnSequentialLogic1.svg}} </WRAP>
  
-The principle interior of the blackbox in <imgref pic04> was already shown in one practical application in the [[:introduction_to_digital_systems:storage_elements#look_onto_the_problem_reduce_it_down_to_the_relevant_part|previous chapter]]: We saw, that we need the combination of an combinatorial logic and some storage components. Additionally, both have to be connected by feeding back some of the outputs back to the combinatorial logic. The output bits $\vec{Y}$ can result either from the combinatorial logic or the flip-flops. This is shown in <imgref pic05>.+The principle interior of the black box in <imgref pic04> was already shown in one practical application in the [[:introduction_to_digital_systems:storage_elements#look_onto_the_problem_reduce_it_down_to_the_relevant_part|previous chapter]]: We saw, that we need the combination of combinatorial logic and some storage components. Additionally, both have to be connected by feeding back some of the outputs back to the combinatorial logic. The output bits $\vec{Y}$ can result either from the combinatorial logic or the flip-flops. This is shown in <imgref pic05>.
  
 <WRAP> <imgcaption pic07| One Step more into the Sequential Logic> </imgcaption> {{drawio>ViewOnSequentialLogic2.svg}} </WRAP> <WRAP> <imgcaption pic07| One Step more into the Sequential Logic> </imgcaption> {{drawio>ViewOnSequentialLogic2.svg}} </WRAP>
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-One simple example of a sequential logic is shown in <imgref pic09>. There, the combnatorial logic is explicitely shown. Depending on the input $X$ the output $\vec{Y}$ shows an up-counting 2-bit value counting $0 \rightarrow 1 \rightarrow 2 \rightarrow 3 \rightarrow 0 \rightarrow ...$. This is a simple state machine which will be used in the net chapters+One simple example of sequential logic is shown in <imgref pic09>. There, the combinatorial logic is explicitly shown. Depending on the input $X$ the output $\vec{Y}$ shows an up-counting 2-bit value counting $0 \rightarrow 1 \rightarrow 2 \rightarrow 3 \rightarrow 0 \rightarrow ...$. This is a simple state machine that will be used in the net chapters
  
 <WRAP><well> <imgcaption pic09|State machine of an Up-Counter></imgcaption>\\ <WRAP><well> <imgcaption pic09|State machine of an Up-Counter></imgcaption>\\
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 ===== 6.2 Classical State Machine Types ===== ===== 6.2 Classical State Machine Types =====
  
-The up-counter in the previous sub-chapter was able to count from $0$ to $3$. But what can we do in order to count differently, like $ 7, 6, 1, 5$? In order to understand this, a simplier situation will be investigated. So, let's look how one can create a up-counter counting $1, 2, 3, 4$.+The up-counter in the previous sub-chapter was able to count from $0$ to $3$. But what can we do in order to count differently, like $ 7, 6, 1, 5$? In order to understand this, a simpler situation will be investigated. So, let's look at how one can create an up-counter counting $1, 2, 3, 4$.
  
 ==== 6.2.1 Moore Machine ==== ==== 6.2.1 Moore Machine ====
  
-The first idea might be to use what we already have: an up-counter, which faciliate 2 flip-flops in order to result into 2-bit output. +The first idea might be to use what we already have: an up-counter, which facilitates 2 flip-flops in order to result in 2-bit output. 
-The wanted new state machine needs 3 bits for the output, since the binary representation of our outputs are $001_2$,$010_2$,$011_2$,$100_2$.+The wanted new state machine needs 3 bits for the output, since the binary representation of our outputs is $001_2$,$010_2$,$011_2$,$100_2$.
  
-An simple idea is to take the 2-bit up-counter and add an combinatorial logic in behind. This logic shall convert the 2-bit up-counter output $00_2$ into $001_2$, the $01_2$ into $010_2$, $10_2$ into $011_2$ and $11_2$ into $101_2$. This can be logic can be created by:+A simple idea is to take the 2-bit up-counter and add a combinatorial logic in behind it. This logic shall convert the 2-bit up-counter output $00_2$ into $001_2$, the $01_2$ into $010_2$, $10_2$ into $011_2$ and $11_2$ into $101_2$. This can be logic can be created by:
   * writing down the truth table   * writing down the truth table
   * putting the values into a Karnaugh map   * putting the values into a Karnaugh map
-  * extracting the formula with view onto the implicants+  * extracting the formula with a view onto the implicants
   * generating the circuit with gates    * generating the circuit with gates 
  
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-This resembles a so called **Moore Machine**+This resembles a so-called **Moore Machine**.
  
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-A state machine is a **Moore Machine**, when the output values $\vec{Y}$ depends only on the state values $\vec{Z}$. For this the moore machine uses two combinatorial circuits: +A state machine is a **Moore Machine**when the output values $\vec{Y}$ depend only on the state values $\vec{Z}$. For this the Moore machine uses two combinatorial circuits: 
-  * The input circuit, which process the input values $\vec{X}(n+1)$ and the state values $\vec{Z}(n)$ (of the previous step) in such a way that the new states $\vec{Z}(n+1)$ are generated.+  * The input circuit, which processes the input values $\vec{X}(n+1)$ and the state values $\vec{Z}(n)$ (of the previous step) in such a way that the new states $\vec{Z}(n+1)$ are generated.
   * The output circuit, which transform the state values $\vec{Z}(n)$ into the output values $\vec{Y}(n)$.   * The output circuit, which transform the state values $\vec{Z}(n)$ into the output values $\vec{Y}(n)$.
  
-The properties of a moore machine are: +The properties of a Moore machine are: 
-  * The number of flip-flops is only given by number of states $m$.  +  * The number of flip-flops is only given by the number of states $m$.  
-  * The output only changes when an edge on the clock input happen. The moore machine is a **synchronous state machine**. +  * The output only changes when an edge on the clock input happens. The Moore machine is a **synchronous state machine**. 
-  * The moore machine usually need less logic gates. But this comes with the cost of optimizing two combinatorial logic circuits. +  * The Moore machine usually needs fewer logic gates. But this comes with the cost of optimizing two combinatorial logic circuits. 
  
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 ==== 6.2.2 Mealy Machine ==== ==== 6.2.2 Mealy Machine ====
  
-When looking onto <imgref pic21> a bit more in detail, one can see, that the outputs $Y_0$ and $Y_1$ just equals output of the first combinatorial logic circuit. This is not surprising: the input logic circuit shows the $\vec{Z}(n+1)$ and this is for the counter always the stored value plus one, except when the maximum is reached. +When looking at <imgref pic21> a bit more in detail, one can see, that the outputs $Y_0$ and $Y_1$ just equals the output of the first combinatorial logic circuit. This is not surprising: the input logic circuit shows the $\vec{Z}(n+1)$ and this is for the counter always the stored value plus one, except when the maximum is reached. 
  
-With this information the state machine in <imgref pic21> can be simplified by using the outputs of the input circuit for $Y_0$ and $Y_1$. This is shown in <imgref pic22>.+With this information, the state machine in <imgref pic21> can be simplified by using the outputs of the input circuit for $Y_0$ and $Y_1$. This is shown in <imgref pic22>.
  
 <WRAP><well> <imgcaption pic22| Up-Counter 1..4 as a Mealy Machine ></imgcaption>\\ <WRAP><well> <imgcaption pic22| Up-Counter 1..4 as a Mealy Machine ></imgcaption>\\
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-A state machine is a **Mealy Machine**, when the output values $\vec{Y}$ depends not only on the state values $\vec{Z}$. For this the mealy machine uses two combinatorial circuits: +A state machine is a **Mealy Machine**when the output values $\vec{Y}$ depend not only on the state values $\vec{Z}$. For this the mealy machine uses two combinatorial circuits: 
-  * The input circuit, which process the input values $\vec{X}(n+1)$ and the state values $\vec{Z}(n)$ (of the previous step) in such a way that the new states $\vec{Z}(n+1)$ are generated. +  * The input circuit, which processes the input values $\vec{X}(n+1)$ and the state values $\vec{Z}(n)$ (of the previous step) in such a way that the new states $\vec{Z}(n+1)$ are generated. 
-  * The output circuit, which transform the state values $\vec{Z}(n)$ __and__ some inputs from ahead of the flip-flops into the output values $\vec{Y}(n)$.+  * The output circuit, which transforms the state values $\vec{Z}(n)$ __and__ some inputs from ahead of the flip-flops into the output values $\vec{Y}(n)$.
  
 The properties of a mealy machine are: The properties of a mealy machine are:
-  * The number of flip-flops is only given by number of states $m$.  +  * The number of flip-flops is only given by the number of states $m$.  
-  * The output **not** only changes when an edge on the clock input happen: It is also dependent on the input $\vec{X}(n)$. The mealy machine is an **__asynchronous__ state machine**. +  * The output **not** only changes when an edge on the clock input happens: It is also dependent on the input $\vec{X}(n)$. The mealy machine is an **__asynchronous__ state machine**. 
-  * The mealy machine usually need less logic gates. +  * The mealy machine usually needs fewer logic gates. 
   * The mealy machine has to be designed properly in order not to get invalid outputs.   * The mealy machine has to be designed properly in order not to get invalid outputs.
  
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-A state machine is a **Medvedev Machine**, when the output values $\vec{Y}$ is directly given by the state values $\vec{Z}$. For this the medvedev machine uses only one combinatorial circuit. This circuitprocess the input values $\vec{X}(n+1)$ and the state values $\vec{Z}(n)$ (of the previous step) in such a way that the new states $\vec{Z}(n+1)$ and the output values $\vec{Y}(n+1)= \vec{Z}(n+1)$ are generated.+A state machine is a **Medvedev Machine**when the output values $\vec{Y}$ are directly given by the state values $\vec{Z}$. For this, the Medvedev machine uses only one combinatorial circuit. This circuit process the input values $\vec{X}(n+1)$ and the state values $\vec{Z}(n)$ (of the previous step) in such a way that the new states $\vec{Z}(n+1)$ and the output values $\vec{Y}(n+1)= \vec{Z}(n+1)$ are generated.
  
-The properties of a medvedev machine are: +The properties of a Medvedev machine are: 
-  * The number of flip-flops is given by number of outputs $l$. +  * The number of flip-flops is given by the number of outputs $l$. 
   * The output only changes when an edge on the clock input happens: The mealy machine is an **__synchronous__ state machine**.   * The output only changes when an edge on the clock input happens: The mealy machine is an **__synchronous__ state machine**.
-  * The medvedev machine usually need more logic gates. +  * The Medvedev machine usually need more logic gates. 
  
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   * Number of bits $i$ of states $Z_i$ is given in the legend. The number of bits $i$ has also to fit to the number of states.   * Number of bits $i$ of states $Z_i$ is given in the legend. The number of bits $i$ has also to fit to the number of states.
-  * Here the legend give $Z_2, Z_1, Z_0$, so 3 bits.+  * Here the legend shows $Z_2, Z_1, Z_0$, so there are 3 bits.
   * Also the number of states i the diagram are 5. This can only be numbered with at least 3 bits.    * Also the number of states i the diagram are 5. This can only be numbered with at least 3 bits. 
  
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 +Check for each line:
 +  * What is the start/present state (given by the bits $\color{red}{Z_2(n), Z_1(n), Z_0(n)}$ in the line)? 
 +  * Which transition is shown start/present state (given by $\color{brown}{X_1, X_0}$)? 
 +Out of this orientation, the next columns can be derived:
 +  * At the end of the transition, the next state can be found (necessary for columns $\color{green}{Z_2(n+1), Z_1(n+1), Z_0(n+1)}$)
 +  * Within the state symbol of the present state, the output valuse can be found  (necessary for columns $\color{violet}{Y_2(n), Y_1(n), Y_0(n)}$)
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-{{drawio>STTexample1_solution.svg}} 
- 
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   * Draw the state transition diagram and the state transition table   * Draw the state transition diagram and the state transition table
   * Use alternatively the structure of a 3bit up-counter    * Use alternatively the structure of a 3bit up-counter 
-    * Draw the structure of this moore machine with the up-counter as a blackbox, the input and output values and - if necessary - further blackboxes+    * Draw the structure of this Moore machine with the up-counter as a blackbox, the input and output values and - if necessary - further blackboxes
     * draw and fill in the additional table.      * draw and fill in the additional table. 
  
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-  * Draw the state transition diagram of the moore machine of the synchronous sequential circuit.+  * Draw the state transition diagram of the Moore machine of the synchronous sequential circuit.
   * Create the digital ciruit.   * Create the digital ciruit.
  
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 {{drawio>ExLED.svg}} {{drawio>ExLED.svg}}
  
-  * Draw the state transition diagram of the moore machine of the synchronous sequential circuit.+  * Draw the state transition diagram of the Moore machine of the synchronous sequential circuit.
   * Create the digital ciruit.   * Create the digital ciruit.
  
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 Develop a sequential circuit, which generate a clock driven up-counter from $1..6$. The not reqired states shall lead after one clock cycle to the state of number $1$. Develop a sequential circuit, which generate a clock driven up-counter from $1..6$. The not reqired states shall lead after one clock cycle to the state of number $1$.
  
-  * Draw the state transition diagram of the moore machine of the synchronous sequential circuit.+  * Draw the state transition diagram of the Moore machine of the synchronous sequential circuit.
   * Create the digital ciruit.   * Create the digital ciruit.
  
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