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introduction_to_digital_systems:sequential_logic [2024/12/10 12:14] – [6.2.2 Mealy Machine] mexleadminintroduction_to_digital_systems:sequential_logic [2024/12/17 09:37] (aktuell) mexleadmin
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   * The **output vector** $\vec{Y}$ represents the $l$ outputs $Y_0 ... Y_{l-1}$.   * The **output vector** $\vec{Y}$ represents the $l$ outputs $Y_0 ... Y_{l-1}$.
   * The **state vector** $\vec{Z}$ represents the $m$ inputs $Z_0 ... Z_{m-1}$.   * The **state vector** $\vec{Z}$ represents the $m$ inputs $Z_0 ... Z_{m-1}$.
-  * The sign $(n)$ or $n$ marking the current point in time and therefore e.g. the current state $Z_0(n)$. +  * The subscript $(n)$ or $n$ marking the current point in time and therefore e.g. the current state $Z_0(n)$. 
-  * The sign $(n+1)$ or $n+1$ marking the next upcoming point in time and therefore e.g. the next state $Z_0(n+1)$.+  * The subscript $(n+1)$ or $n+1$ marking the next upcoming point in time and therefore e.g. the next state $Z_0(n+1)$.
   * Sequential logic circuits are also called **Finite State Machines** (FSM) or sometimes also shortened to "state machines".   * Sequential logic circuits are also called **Finite State Machines** (FSM) or sometimes also shortened to "state machines".
  
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 <WRAP><well> <imgcaption pic23| Up-Counter 1..4 as a Medvedev Machine ></imgcaption>\\ <WRAP><well> <imgcaption pic23| Up-Counter 1..4 as a Medvedev Machine ></imgcaption>\\
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 The <imgref pic101> shows the principle differences in the architecture of the state machines. The <imgref pic101> shows the principle differences in the architecture of the state machines.
  
-<WRAP> <imgcaption pic101| States of Water> </imgcaption> {{drawio>differencesinSM.svg}} </WRAP>+<WRAP> <imgcaption pic101| Compariston of State Machine Types> </imgcaption> {{drawio>differencesinSM.svg}} </WRAP>
  
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