Unterschiede
Hier werden die Unterschiede zwischen zwei Versionen angezeigt.
| Beide Seiten der vorigen Revision Vorhergehende Überarbeitung Nächste Überarbeitung | Vorhergehende Überarbeitung | ||
| introduction_to_digital_systems:sequential_logic [2024/12/10 12:15] – [6.2.3 Medvedev Machine] mexleadmin | introduction_to_digital_systems:sequential_logic [2024/12/17 09:37] (aktuell) – mexleadmin | ||
|---|---|---|---|
| Zeile 16: | Zeile 16: | ||
| * The **output vector** $\vec{Y}$ represents the $l$ outputs $Y_0 ... Y_{l-1}$. | * The **output vector** $\vec{Y}$ represents the $l$ outputs $Y_0 ... Y_{l-1}$. | ||
| * The **state vector** $\vec{Z}$ represents the $m$ inputs $Z_0 ... Z_{m-1}$. | * The **state vector** $\vec{Z}$ represents the $m$ inputs $Z_0 ... Z_{m-1}$. | ||
| - | * The sign $(n)$ or $n$ marking the current point in time and therefore e.g. the current state $Z_0(n)$. | + | * The subscript |
| - | * The sign $(n+1)$ or $n+1$ marking the next upcoming point in time and therefore e.g. the next state $Z_0(n+1)$. | + | * The subscript |
| * Sequential logic circuits are also called **Finite State Machines** (FSM) or sometimes also shortened to "state machines" | * Sequential logic circuits are also called **Finite State Machines** (FSM) or sometimes also shortened to "state machines" | ||
| Zeile 134: | Zeile 134: | ||
| The <imgref pic101> shows the principle differences in the architecture of the state machines. | The <imgref pic101> shows the principle differences in the architecture of the state machines. | ||
| - | < | + | < |
| \\ \\ | \\ \\ | ||