DW EditSeite anzeigenÄltere VersionenLinks hierherAlles aus-/einklappenNach oben Diese Seite ist nicht editierbar. Sie können den Quelltext sehen, jedoch nicht verändern. Kontaktieren Sie den Administrator, wenn Sie glauben, dass hier ein Fehler vorliegt. CKG Editor ====== 6. Sequential Logic ====== "I Know What You Did Last Cycle" ===== 6.1 First Terminology ===== Sequential logic is used to describe logic cicruits which show internal states ("stateful"), and therefore have at least one memory element (= flip-flop). The following terminology is used in the upcoming explanations: * The **input vector** $\vec{X}$ represents the $k$ inputs $X_0 ... X_{k-1}$ * The **output vector** $\vec{Y}$ represents the $l$ outputs $Y_0 ... Y_{l-1}$ * The **state vector** $\vec{Q}$ represents the $m$ inputs $X_0 ... X_{m-1}$ * The sign $(n)$ or $n$ marking the current point in time and therefore e.g. the current state $Q_0(n)$ * The sign $(n+1)$ or $n+1$ marking the next upcomming point in time and therefore e.g. the next state $Q_0(n+1)$ * Sequential logic circuits are also called **Finite State Machines** (FSM) or sometimes also shortened to "state machine" The <imgref pic04> shows the different terms in an abstract diagram. The "current" output values are here the values, which are shown after the delay time of the gates (about some nanoseconds). <WRAP> <imgcaption pic06| Abstract View onto a Sequential Logic> </imgcaption> {{drawio>ViewOnSequentialLogic1}} </WRAP> The principle interior of the blackbox in <imgref pic04> was already shown in one practical application in the [[:introduction_to_digital_systems:storage_elements#look_onto_the_problem_reduce_it_down_to_the_relevant_part|previous chapter]]: We saw, that we need the combination of an combinatorial logic and some storage components. Additionally, both have to be connected by feeding back some of the outputs back to the combinatorial logic. The output bits $\vec{Y}$ can result either from the combinatorial logic or the flip-flops. This is shown in <imgref pic05>. <WRAP> <imgcaption pic07| One Step more into the Sequential Logic> </imgcaption> {{drawio>ViewOnSequentialLogic2}} </WRAP> <panel type="info" title="Exercise 6.1.3.1 Example of a State Machine"> <WRAP group><WRAP column 2%>{{fa>pencil?32}}</WRAP><WRAP column 92%> <imgref pic06> depicts a state machine. * What happens, when $X$ is changed? On which edge the change is triggered? * Write down how many components each vector $\vec{X}$ and $\vec{Y}$ has. * How many might the state vector $\vec{Q}$ need? <WRAP><well> <imgcaption pic08|Example for a sequential logic></imgcaption>\\ {{url>https://www.falstad.com/circuit/circuitjs.html?hideSidebar=true&ctz=CQAgjCAMB0l3BWcMBMcUHYMGZIA4UA2ATmIxAUgpABZsKBTAWjDAChoQBhAewFcAdgBcGAJyggUk2twAyAaRkQpADRB4JUgJpVC4EPS3KJ9ACIAxADYBLAA5WetgKKWAtgB0AzmC8ov2Lxp3UQsbe0tHFw9PBC9CLwxA4IBBAQATAHEAQxEouK88L2JglR5RbNy3It8vH1FS8pyGPM94z0KYqHcvSB7umL6awYHPXqHR-tiJ8divBDYaMCoUFBpJfEkMKVWqCF5BEXFe0a6T478JzvO+q5rL+YAlSVXJGl2MPR39KSXl6CQUP8JDB5otiAZCBowDQ1os9NC1lQaGwAO4GNCvKjYSGYqCo9HLDbYjRoDSQNiyZ5rUngD7rEkSABmWUsngY1HJAA9acoyOA8ORcEjXiAVGxuWAMMsMOCwMRqQQZC9AEmE4oM2GUeCxCABeHo1LWqu52Gw22IGmwNAtkAgBpAWjYQA noborder}} </well></WRAP> </WRAP></WRAP></panel> One simple example of a sequential logic is shown in <imgref pic09>. There, the combnatorial logic is explicitely shown. Depending on the input $X$ the output $\vec{Y}$ shows an up-counting 2-bit value counting $0 \rightarrow 1 \rightarrow 2 \rightarrow 3 \rightarrow 0 \rightarrow ...$. This is a simple state machine which will be used in the net chapters <WRAP><well> <imgcaption pic09|State machine of an Up-Counter></imgcaption>\\ {{url>https://www.falstad.com/circuit/circuitjs.html?hideSidebar=true&ctz=CQAgjCAMB0l3BWcMBMcUHYMGZIA4UA2ATmIxAUgpABZsKBTAWjDACgwEls1xCrsCFHyqiOXEDyqZhg4TKhRxVVsLAZC4DVs3TFCcTRBo8I4xjX9Fwqgc5GT5+RafX9bGino1CRmmE0aU39dDy9aX0lCYNNsaKVPb1j4oMkhBPDUuUVsPFNIMPoBPNpg3Ayk2nLUkIqIozjgyNqCgHdXAIFeTqV2qVcFBTbjfB0x9VD22oUg6Rdh2p6aYk0ehbxpEtnJPCN14r2dvbYpleMEQLOaOF7aK5uWQJvhxzAaP1M34-bHFC3TP75E4jAEXECRFBggoAJRATA2kkgRhYYFkSPAxmQ0mgSBQOMUMAMABk4ZEeijLHoqAAzACGABsAM4MajDeECdG4Bro4Zc8DEWTdAW3PlgYV8vm8zmc3iS4FMMlWRVidrK8CoszDNUQqHAg6KMU2eUBWgPE1fW6PcDvUrW74G4WpQ23J3C1T8o1TT6OgElAr+Yjg0bOwguZ1UGjA-igy6aSGhABGkjUGpQ4vKBST-nogliKAg7oWZ3jd1WVgKaHICqM5LJf1oIAAGmxK6U5sJtihrg2AIoVyDkaPnTQIYVdiMgACa7AAHsma5BvOiwJBAsYjIyAC4AewATrSAOYMNhzhD0DAAyBqUYOIwAY23AFsEwBLAB2tJ3u5fDIAOozf1-N87xfXc7wAVxfTd-xPKpVkXUpPlXBsuxALdP2POdCHrFd6BIBc11Q7dwM3AAHEiWwHINfVMUdnA7Kd9mMf52xdBFAWo5igVbZYywjM5UWCEAe3YIA noborder}} </well></WRAP> ===== 6.2 Classical State Machine Types ===== The up-counter in the previous sub-chapter was able to count from $0$ to $3$. But what can we do in order to count differently, like $ 7, 6, 1, 5$? In order to understand this, a simplier situation will be investigated. So, let's look how one can create a up-counter counting $1, 2, 3, 4$. ==== 6.2.1 Moore Machine ==== The first idea might be to use what we already have: an up-counter, which faciliate 2 flip-flops in order to result into 2-bit output. The wanted new state machine needs 3 bits for the output, since the binary representation of our outputs are $%001$,$%010$,$%011$,$%100$. An simple idea is to take the 2-bit up-counter and add an combinatorial logic in behind. This logic shall convert the 2-bit up-counter output $%00$ into $%001$, the $%01$ into $%010$, $%10$ into $%011$ and $%11$ into $%101$. This can be logic can be created by: * writing down the truth table * putting the values into a Karnaugh map * extracting the formula with view onto the implicants * generating the circuit with gates When this is done, the result looks like <imgref pic21> <WRAP><well> <imgcaption pic21| Up-Counter 1..4 as a Moore Machine ></imgcaption>\\ {{url>https://www.falstad.com/circuit/circuitjs.html?hideSidebar=true&ctz=CQAgjCAMB0l3BWcMBMcUHYMGZIA4UA2ATmIxAUgpABZsKBTAWjDACgwEls1xCrsCFHyqiOXEDyqZhg4TKhRxVVsLAZC4DVs3TFCcTRBo8I4xjX9Fwqgc5GT5+RafX9bGino1CRmmE0aU39dDy9aX0lCYNNsaKVPb1j4oMkhBPDUuUVsPFNIMPoBPNpg3Ayk2nLUkIqIozjgyNqCgHdXAIFeTqV2qVcFBTbjfB0x9VD22oUg6Rdh2p6aYk0ehbw54VnJPCN14r2dvbYpleMaKmXAuF7aM4uqFmuxdscwGj9Td+PX0ZQS1L-fInEamFAITSRcGhABKICYG0kkCMLDAsmR4GMyGk0CQKFxihgBgAMvDIj1UZY9FQAGYAQwANgBnBjUYYIgQY3ANDHDbngYiybqC278sAi-n8vlcrm8KUgpjkqxKl4gFXgNFmYbqqEQ24HRTimwKgK0G5PcAfW4W76lS0-Q0i1JG27OkWqAXGqZfJ1gkoFfzEEAYdIuvCml2XEGEPUoFBGEPyeO3RPGPUxzTQpQAI0kak1KAl5QKuf89EEsRQEA9CzO8cuZzWbDQ5EVRgp5P+tBAAA1m5ByFczEO0cEQABFdgt0qbGfnS4TgrT1NxhNxUHdgCaKH75BXepwmYuW-YAA88+3IN4MWBIIFziAmQAXAD2ACc6QBzBhsc8IegYGC7zIGOyYAMYvgAttmACWAB2dKvm+MFgYyAA6TJoWhcFgTBb5gQArjBT4YWeVSrFepRfHe3bJs+iE-ueWBqJReC5Mg97Ji+BFPgADjxygUFYExqsmInUhQhgUCKWYZmmuhYrYIIQioVgIFaTbtOp7ZWCOVjDNpZiGfWtzGceCAyce+yuEIYLzMpXYKBZzhekJKgirZnqmV2LqeUM0axsmcniQFqzaIQYnaAUf5gKYWBqhgQa3oOD4QdB8GIe+KHoZh2G4fhREkUyO65ggsUakYhBVZIPBKMu6RAsG64zCAm4FAAkhQVr8s5SKHESklaY5LiefKQ2xBihljdJ6KVXq01yfycmNdqsYlCu-psEAA noborder}} </well></WRAP> This resembles a so called **Moore Machine** <WRAP column 100%> <panel type="danger" title="Note!"> <WRAP group><WRAP column 7%>{{fa>exclamation?32}}</WRAP><WRAP column 80%> A state machine is a **Moore Machine**, when the output values $\vec{Y}$ depends only on the state values $\vec{Q}$. For this the moore machine uses two combinatorial circuits: * The input circuit, which process the input values $\vec{X}(n+1)$ and the state values $\vec{Q}(n)$ (of the previous step) in such a way that the new states $\vec{Q}(n+1)$ are generated. * The output circuit, which transform the state values $\vec{Q}(n)$ into the output values $\vec{Y}(n)$. The properties of a moore machine are: * The number of flip-flops is only given by number of states $m$. * The output only changes when an edge on the clock input happen. The moore machine is a **synchronous state machine**. * The moore machine usually need less logic gates. But this comes with the cost of optimizing two combinatorial logic circuits. </WRAP></WRAP></panel> </WRAP> ==== 6.2.2 Mealy Machine ==== When looking onto <imgref pic21> a bit more in detail, one can see, that the outputs $Y_0$ and $Y_1$ just equals output of the first combinatorial logic circuit. This is not surprising: the input logic circuit shows the $\vec{Q}(n+1)$ and this is for the counter always the stored value plus one, except when the maximum is reached. With this information the state machine in <imgref pic21> can be simplified by using the outputs of the input circuit for $Y_0$ and $Y_1$. This is shown in <imgref pic22>. <WRAP><well> <imgcaption pic22| Up-Counter 1..4 as a Mealy Machine ></imgcaption>\\ {{url>https://www.falstad.com/circuit/circuitjs.html?hideSidebar=true&ctz=CQAgjCAMB0l3BWcMBMcUHYMGZIA4UA2ATmIxAUgpABZsKBTAWjDACgwEls1xCrsCFHyqiOXEDyqZhg4TKhRxNEGjyS8Khdk2LhSBGxop6OpITogm2CBfqQjJjQeJJrEBK6XH67il78EDGJvJ0DgqwjCTlDfKJi-QiDYqxsQJPJEywcfZ39uPHNstgB3VQxhMH5JXiqxMtwtCvL5ZocymiqW2jxpNtLaLrraYkIRJQ7e7popnRV2nqoEGhUmUYoViZGxlBQVGnWaOC2DsYRqljB9aocAJSsr9U6xlmrn8FVkaWgkFB-FGCGAAyVhQeHUj1S2DGkOEVAAZgBDAA2AGcGNQFiwwYMxlJcVt8WBiLJeI1vMSQBghOASSA8EM6VQaANTqo9lSabt5gNqfJzhQrqoBQ4AEbgeiseR4EI0DA88WdehygQoCBSk7rbnbcYONCZMEQnFMQ0gQ4gAAabH1OuGbMhKgAiihrZByCt1HNaDNJDSnXq3Zz5BycDt8LQQABNF02vnCsah1RHCOR9gADxqKjAkGVkCzkDGWhUqIALgB7ABOiIA5gw2BmEPQMOo1fmnkmQABjMsAW1FAEsAHaI8sV-udlEAHVRk8ng87-YrnYArv2S9P07RochleDkIWO6WR3WM1hKjn6Tp9xGOWXlyWAA731lTBQIIUKAPkOOmxMKFSRgs77SuoP57gs5LaLwn7iNwZK6HIGjzBQrJdF6HpIScXQYXQwgYQsuHek8PA6gRsy6DMSybARhzHGy5xiDalHTK+yZOuwHQ+kczI+sBJwWBQxpTEI6gESRbJMFx6xAR+zR8SgIoDPJe58dxWyqXRXHHARWk8Z6ugQWSeY1MyXSGQIujaAZAxqLQxxMAJakOJwVBDJs6xgNRnxLOI8jhsMCjDNIiiGJwfkts0CifpIIXiK5QrEpUdKJXosUuXwqjhlq4bBT5ZQeZstmeTyZQpWAGBhhCFVbGV1VlUyAwauVLyms1NUflllVKOlGoKTCdJ9aleW0vyXWDc5lAZaaWrgd5KE9XiNLrIhwUGHF4BCtg24pVtYy5ShZS2dCVV4oQomNdVx3gJd1mlTdqyml6WK6VYUl7Y1Owcg5Wgcs9Tz2T65JYusyyrFq-RlJclTVEMNwfSNVgeQ1kOzGdVjCTiCy9cmJocns9Rml14NwgMxMba0JOlZtvAmnu+JY5tS2LZTCO7QjppYwNe62RzNnhoF1UwflOx7m1vN3SLJ3dFjOzNGssss99dlUErfEEWh240AJbMEdrmsCSJJy8UKqtCliGoMQ8CVw5DAkKEr2oy+AxrapCTvkpJnrGcDCuI-1iuoxCp3naVeLbkrOsDBH4d2-0ACSoKiy7HJu1A-yGJDrvJ0WBO00a6h59d72Z6L1WF-TUePTTj23VYjn2Xr71AA noborder}} </well></WRAP> <WRAP column 100%> <panel type="danger" title="Note!"> <WRAP group><WRAP column 7%>{{fa>exclamation?32}}</WRAP><WRAP column 80%> A state machine is a **Mealy Machine**, when the output values $\vec{Y}$ depends not only on the state values $\vec{Q}$. For this the mealy machine uses two combinatorial circuits: * The input circuit, which process the input values $\vec{X}(n+1)$ and the state values $\vec{Q}(n)$ (of the previous step) in such a way that the new states $\vec{Q}(n+1)$ are generated. * The output circuit, which transform the state values $\vec{Q}(n)$ __and__ some inputs from ahead of the flip-flops into the output values $\vec{Y}(n)$. The properties of a mealy machine are: * The number of flip-flops is only given by number of states $m$. * The output **not** only changes when an edge on the clock input happen: It is also dependent on the input $\vec{X}(n)$. The mealy machine is an **__asynchronous__ state machine**. * The mealy machine usually need less logic gates. * The mealy machine has to be designed properly in order not to get invalid outputs. </WRAP></WRAP></panel> </WRAP> <panel type="info" title="Exercise 6.2.2.1 Invalid States of the Mealy Machine"> <WRAP group><WRAP column 2%>{{fa>pencil?32}}</WRAP><WRAP column 92%> The mealy machine in <imgref pic22> can show invalid outputs. Try to find these by the correct timing of the input $X=1$ or $X=0$. * Which outputs can be created? </WRAP></WRAP></panel> ==== 6.2.3 Medvedev Machine ==== <WRAP><well> <imgcaption pic23| Up-Counter 1..4 as a Medvedev Machine ></imgcaption>\\ {{url>https://www.falstad.com/circuit/circuitjs.html?hideSidebar=true&ctz=CQAgjCAMB0l3BWcMBMcUHYMGZIA4UA2ATmIxAUgpABZsKBTAWjDACgwEls1xCrsCFHyqiOXEDyqZhg4TKgVxNEGjyS8Khdk2LhVBGxop6OpITogm2CBfqQjJjUgTEk1iK6QPj9DxTcrGwoMYihHP2CEUKsYwk5w31iw+PdgwmjEp38M8hzLHyczAO48cwK2AHdVDGEwfkleerFq3C1amvkOh2qaes7aPGluqtp+5tpiQhFw3qGBmnmdFR7BgxoVJimKDdnJ6ZQUFRptmjg9k+mEBpYwYWuxACUrO-U+6ZYG9-BVZGloJAoAGKGCGAAyVhQeHUryC2GmsLqIAAZgBDAA2AGcGNRViwoWNplJCXtiWBiLJeG1EuSQBghOAKSA8OMmVQaKNLqojnSGYcVqN6fJrhQ7qoRQ4AEbgeiseR4MI0DAC6V9ehKgQoCByi7bfn7GYONB5KEwglMU0gU4gAAabGNBomXNhKgAiih7ZByBt1MtaItJAy3Uavbz5DycAd8LQQAAtD0OoXi6aR1RnGOx9gAD0aKjAkHVkDzkGmWhUmIALgB7ABOqIA5gw2DmEPQMOotcW3mmQABjKsAW0lAEsAHao6s14e9jEAHUxs9no97w5rvYArsOK-Ps7R4ch1dDkKWe5WJ02c1g6gXmTpjzGeVX1xWAA7PznzBQIMUKEPkJOWqmCgqLGqzfvK6gAUeqzUtovC-uI3BUrocgaCsSi9P0fo+mhFz9DhdDCDhqyEf6bw8AaJFLLoizrAKvSnOcXIPOEDq0Qsn7pm67C9AGZzsgG4EXBYFDmvMQjqCRFFckwfHbGBP4dEJKASqMylHkJ-F7JpTF8ecJF6QJvq6DBVJFo07L9KZAi6NoJmjGotDnEwIlaQ4nBUOMuzbGAuzSIohicPI0YTAoEz+S44jBR2HQKL+kgBeInliuSdRMqlejUIFlB8Ko0Z6tGEUYVaCK7I5vn0YydQYFGMI1XsGVgPVjVsqMOpNR8lodQ1P75bV4QeeAP4ihlKnTP5BhtUyY15R2qmDf0lp6tBvyTQtRIMtsqETUoC1itg+4ZQd42rcVjnwnVRKEJJbX1Rd4B3fZ1TdX6FpHn6eKGVYcnjW1Bw8i5Wg8p9bzOQG1J4tsCC7FsBwjNUtx1A04wNKsrLCLDVV7EwSzXVY4kEmjP7phaPJHC0JWzZTCHVHqHQ6jTQ2UlQb2+rwROyJtG36FNsiHdN0G86oR6OZaqyi-T9WM8tl3Czdz1S0e3WM4tHSY4zgNOSzIlCSRWH7jQInHcJKjG4bKgSRcglipruujIjFA3O1qP2yJCia-qaMIua+qwl7kjmbJvrmZDcMYz5rUI7jMJXfLuXG5rxt4kb+4eyMACSkJKz7PJ+1AwKGAjvs52WFOs+APtK-VeJdfV5fEjX728PXT1WK5zkp79QA noborder}} </well></WRAP> <WRAP column 100%> <panel type="danger" title="Note!"> <WRAP group><WRAP column 7%>{{fa>exclamation?32}}</WRAP><WRAP column 80%> A state machine is a **Medvedev Machine**, when the output values $\vec{Y}$ is directly given by the state values $\vec{Q}$. For this the medvedev machine uses only one combinatorial circuit. This circuitprocess the input values $\vec{X}(n+1)$ and the state values $\vec{Q}(n)$ (of the previous step) in such a way that the new states $\vec{Q}(n+1)$ and the output values $\vec{Y}(n+1)= \vec{Q}(n+1)$ are generated. The properties of a medvedev machine are: * The number of flip-flops is given by number of outputs $l$. * The output only changes when an edge on the clock input happens: The mealy machine is an **__synchronous__ state machine**. * The medvedev machine usually need more logic gates. </WRAP></WRAP></panel> </WRAP> ===== 6.3 State Diagram, State Transition Diagram ===== ==== 6.3.1 Motivation ==== The diagrams of different states are well known from physics for example the state diagram (or better: phase diagram) of water, where its three states are: solid ice, liquid water and gaseous steam. The possible state transitions are due to temperature increase or decrease. In <imgref pic01> image (1) the states of water are shown on the temperature axis. When only the state transistions are relevant, the states are simplified to a circle, showing the state name and behaviour. The transitions are depict as arrows, where the needed condititon is written onto (See <imgref pic01> image (2) ). This diagram is called **state transition diagram**. <WRAP> <imgcaption pic01| States of Water> </imgcaption> {{drawio>SDwater}} </WRAP> For matter not only the dimension "temperature" is important, but also the "pressure". The full phase diagram is shown in <imgref pic02> image (1). By this, another variable is available and more transistions. These can be drawn into the state transition diagram (<imgref pic02> image (2)). <WRAP> <imgcaption pic02| States of Water> </imgcaption> {{drawio>SDwater2}} </WRAP> ==== 6.3.2 Simple logic Example ==== In German, often one has to pay for entering the toilet. An example of such a entrance control system is shown in <imgref pic03>. At this (artificial) example, one can pay either 50ct or 1€. \\ Once paid, the turnstile will release and one can enter. Once the turnstile was pushed the entrance is closed again. <WRAP> <imgcaption pic03| Entrance Control for Toilets> </imgcaption> {{drawio>EntranceFee}} </WRAP> The <imgref pic04> the state transition diagram is drawn. * The two states are that (1) the turnstile is opened and one is able to go through and (2) the turnstile is closed and one cannot enter anymore. * The transitions are given by the done actions: one can either insert a coin or push on the turnstile. Important here are some additional considerations: * For the state transition diagram one has to **look for all possible transitions**. So, also pushing a closed turnstile or inserting more coins have to taken into account. * A state transition diagram is not complete without a **legend** and without an **beginning/reset point**. The reset point is given by an arrow with "reset" written onto it <WRAP> <imgcaption pic04| State Transition Diagramm of the Entrance Control for Toilets> </imgcaption> {{drawio>STDEntranceFee}} </WRAP> Out of this state transition diagram one can create a table-like representation, see <imgref pic05>. <WRAP> <imgcaption pic05| State Transition Diagramm of the Entrance Control for Toilets> </imgcaption> {{drawio>STDEntranceFee2}} </WRAP> the inputs, outputs and states have to be encoded into binary, in order to investigate this table a bit more. How the binary value is connected to the outputs does not matter. We will choose the following coding: * Encoding of the states: turnstile closed ≙ $Q=0$, turnstile opened ≙ $Q=1$, * Encoding of the inputs: no coin inserted ≙ $Xc=0$, coin inserted ≙ $Xc=1$, turnstile not pushed ≙ $Xp=0$, turnstile pushed ≙ $Xp=1$, * Encoding of the outputs: disallow entrance ≙ $Y=0$, allow entrance ≙ $Y=1$, This table is shown in <imgref pic06> and is called **state transition table**. <WRAP> <imgcaption pic06| State Transition Diagramm of the Entrance Control for Toilets> </imgcaption> {{drawio>STDRSFF}} </WRAP> Interestingly, the logic circuit for this state transition table was already part of the course: it is the RS flip-flop! When looking deeper onto the table in <imgref pic06> one can substitute $Xc$ with $S$ (as in Set) and $Xp$ with $R$ (as in Reset) to directly get the truthtable of the RS flip flop.