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introduction_to_digital_systems:storage_elements [2022/10/18 02:35]
tfischer 		introduction_to_digital_systems:storage_elements [2022/12/03 11:07]
mexleadmin [Bearbeiten - Panel]
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 Data registers are used to hold input and output data of the CPU and peripherals.  Data registers are used to hold input and output data of the CPU and peripherals. 
  
-<panel type="info" title="Exercise 5.3.1. Data Register"> <WRAP group><WRAP column 2%>{{fa>pencil?32}}</WRAP><WRAP column 92%>+<panel type="info" title="Exercise 5.3.1.1 Data Register"> <WRAP group><WRAP column 2%>{{fa>pencil?32}}</WRAP><WRAP column 92%>
  
 Investigate the simulation in <imgref pic050> by toggling the inputs via click on the input value. Investigate the simulation in <imgref pic050> by toggling the inputs via click on the input value.
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 When looking onto the decimal output in <imgref pic052> it seems, that it mostly represents a downcounter. But in detail every second step down and even more every 4th step down (e.g. from ''8'' to ''7'') a glitch shows a wrong value shortly. This is due to the above-mentioned delay by the asynchronous flip-flops. When looking onto the decimal output in <imgref pic052> it seems, that it mostly represents a downcounter. But in detail every second step down and even more every 4th step down (e.g. from ''8'' to ''7'') a glitch shows a wrong value shortly. This is due to the above-mentioned delay by the asynchronous flip-flops.
  
-<panel type="info" title="Exercise 5.3.3. Frequency Divider"> <WRAP group><WRAP column 2%>{{fa>pencil?32}}</WRAP><WRAP column 92%>+<panel type="info" title="Exercise 5.3.3.1 Frequency Divider"> <WRAP group><WRAP column 2%>{{fa>pencil?32}}</WRAP><WRAP column 92%>
  
 Investigate the simulation in <imgref pic052>. Investigate the simulation in <imgref pic052>.