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--- introduction_to_digital_systems:storage_elements [2021/11/24 01:52]
tfischer
+++ introduction_to_digital_systems:storage_elements [2022/12/03 11:07]
mexleadmin [Bearbeiten - Panel]
@@ Zeile 40: / Zeile 40: @@
   * When $S=1$ and $R=1$, it is unclear what to do.
-<WRAP> <imgcaption pic02| truth table for the RS Flip-Flop> </imgcaption> {{drawio>TTflipflop}} </WRAP>
+<WRAP> <imgcaption pic02| truth table for the RS Flip-Flop> </imgcaption> {{drawio>TTflipflop.svg}} </WRAP>
 In <imgref pic02> the last input ($S=1$, $R=1$) reaches a not defined state. This state have to be investigated more later.
@@ Zeile 84: / Zeile 84: @@
 <WRAP><well> <imgcaption pic04|The RS Flip-Flop (based on NOR gates)></imgcaption> \\ {{url>https://www.falstad.com/circuit/circuitjs.html?ctz=CQAgzCAMB0kKxVgRgCxMgTjGAHJA7JEmGnEiHJBSChHAKYC0SSAUAO4ioogBM+vLih68cOKBz6RxvFFW58BEzr2l8kANiky5y7YsELZVSJNUyMW8wb1HZQkbtNI4EI5v28P5QQjisXN2E+S09QnygKVgAPLjB5fBENLSR8fBo+HgA5AHkAJQAdAGcAMwAbAEsAB2LygHsq1gAjOJSMQV44DHBUCVj7eK00cEwM+zyYxXUeWnV0xxAAZVYAGQcRniV4kUiSgEMyovpqUzWjNSVrQSp9w+OEU1jsES9wOA77BYBFSbBOkYgYEoIyGmRAAHofgBZTIWLTbEJWPjQfww2QyDwIrxI3goswoOF8ezYvRXDy8YkeUwqAnqKzE0LUokiUJXRmsIA noborder}} </well></WRAP>
-<WRAP> <imgcaption pic05| The RS Flip-Flop> </imgcaption> {{drawio>RSflipflop}} </WRAP>
+<WRAP> <imgcaption pic05| The RS Flip-Flop> </imgcaption> {{drawio>RSflipflop.svg}} </WRAP>
 ==== 5.1.3 D-Latch - Solving the Inconsistencies ====
@@ Zeile 100: / Zeile 100: @@
 <WRAP><well> <imgcaption pic07|The D Latch></imgcaption> \\ {{url>https://www.falstad.com/circuit/circuitjs.html?ctz=CQAgzCAMB0lwjFa8Cs8BsAOAnOg7LmJpgEzxgogqRUgAsEKApgLTzwBQA7iPHXSBJ4SvfoOJRugyJkF0afAUJGQpJGYIzTZJeZJ7qdw0Ur2qDGkrm2Dj5k4N0PdNVagiLN6G2W+IRlCgc7s7WhoLW-lBUHABGILLw2DQkQuDqkgAeICwoEGQCLGDeZHj0ciAAIhzZYGBKZOAoIqkCpiAAijXplGCQEBQ0fd7tAPRdALJyOtZ9SmGC0EFTujpac16Ci0EGdDMlTr76Plqtm-arm2dW3heHYZbWqgCS6dNvGwoxPGAte2-hNzUBJrPwkUG8LY0IKoGgSG68cERPxQ77ODTwJGAqSYnQYrFaeyeDa48CQAREpEkrFPKS-MkCCSfKTwiTwswsnR6eFOVTZXL5OjeIplXTYcpOACiLJSGnhGlUdFSALlstkrm2MQASirZGwShiti5NSQltEYEEdeyaPq5F8WpRTY6za4lhwAPYA6J0eCQAJIOCQRApD5VD3gfLe33+mCByDYPDoFDoEiUEN1cAgaWe8ion1+2gwYOQro5lpRgtp5DRRDjDhAA noborder}} </well></WRAP>
-<WRAP> <imgcaption pic08| Symbol and truth table of the D-Latch> </imgcaption> {{drawio>DLatch}} </WRAP>
+<WRAP> <imgcaption pic08| Symbol and truth table of the D-Latch> </imgcaption> {{drawio>DLatch.svg}} </WRAP>
 ==== 5.1.4 Edge-Triggered D Flip-Flop - One at a time ====
@@ Zeile 113: / Zeile 113: @@
 <WRAP> <imgcaption pic10| The D Flip-Flop> </imgcaption>
-{{drawio>DFF}} </WRAP>
+{{drawio>DFF.svg}} </WRAP>
 There are some important timing issues of all the flip-flops and latches, which will discussed here. For this, the timing diagram of a positive edge triggered D flip-flop is shown in <imgref pic11>. The upper line depicts the clock $C$, the middle line dhe data $D$ and the lower one the output $Q$.
@@ Zeile 122: / Zeile 122: @@
 <WRAP> <imgcaption pic11| timing of input, clock and output on a Flip-Flop> </imgcaption>
-{{drawio>FFtiming}} </WRAP>
+{{drawio>FFtiming.svg}} </WRAP>
 ==== 5.1.5 JK Flip-Flop - The Alternative to the undefined Behavior ====
@@ Zeile 136: / Zeile 136: @@
 <WRAP> <imgcaption pic14| Symbol and Truth Table of the edge triggered JK Flip-Flop> </imgcaption>
-{{drawio>JKFFtiming}} </WRAP>
+{{drawio>JKFFtiming.svg}} </WRAP>
 ==== 5.1.6 T Flip-Flop - changeable, when wanted ====
@@ Zeile 145: / Zeile 145: @@
 <WRAP> <imgcaption pic16| Symbol and Truth Table of the edge triggered T flip flop> </imgcaption>
-{{drawio>TFFtiming}} </WRAP>
+{{drawio>TFFtiming.svg}} </WRAP>
 ===== 5.2 Convertibility of Flip-Flops =====
@@ Zeile 170: / Zeile 170: @@
 <WRAP> <imgcaption pic18| understanding the problem: JK flip-flop based on a D flip-flop> </imgcaption>
-{{drawio>JKFFbasedonDFFanalysis2}} </WRAP>
+{{drawio>JKFFbasedonDFFanalysis2.svg}} </WRAP>
 The truthtables of the two flip-flops are shown in <imgref pic17>. The relevant (and different) part here is for the rising edge. The other part is similar and does not need further investigation. Since the output $/Q$ always have to be the negation of $Q$, it is only necessary to get the output $Q$ right.
 <WRAP> <imgcaption pic17| understanding the problem: JK flip-flop based on a D flip-flop> </imgcaption>
-{{drawio>JKFFbasedonDFFanalysis}} </WRAP>
+{{drawio>JKFFbasedonDFFanalysis.svg}} </WRAP>
 ==== 5.2.2 Build up a detailed truth table + look onto the relevant outputs ====
@@ Zeile 190: / Zeile 190: @@
 <WRAP> <imgcaption pic19| Creating the truthtable for the JK flip-flop with Q(n+1) as an input> </imgcaption>
-{{drawio>JKFFbasedonDFFtruthtable}} </WRAP>
+{{drawio>JKFFbasedonDFFtruthtable.svg}} </WRAP>
 When looking onto this table, one has now to recap, what the main goal is: What does the combinatorical logic in front of the D flip-flop look like? \\
@@ Zeile 198: / Zeile 198: @@
 <WRAP> <imgcaption pic20| understanding the problem: JK flip-flop based on a D flip-flop> </imgcaption>
-{{drawio>JKFFbasedonDFFlogiccircuit}} </WRAP>
+{{drawio>JKFFbasedonDFFlogiccircuit.svg}} </WRAP>
@@ Zeile 207: / Zeile 207: @@
 <WRAP> <imgcaption pic21| Karnaugh Map for output D based on inputs J, K and Q(n)> </imgcaption>
-{{drawio>JKFFbasedonDFFKmap}} </WRAP>
+{{drawio>JKFFbasedonDFFKmap.svg}} </WRAP>
 The boolean formula for $D$ is therefore: $D=J\cdot\overline{Q(n)} + Q(n)\cdot \overline{K}$. \\
@@ Zeile 304: / Zeile 304: @@
 When looking onto the decimal output in <imgref pic052> it seems, that it mostly represents a downcounter. But in detail every second step down and even more every 4th step down (e.g. from ''8'' to ''7'') a glitch shows a wrong value shortly. This is due to the above-mentioned delay by the asynchronous flip-flops.
-<panel type="info" title="Exercise 5.3.3. Frequency Divider"> <WRAP group><WRAP column 2%>{{fa>pencil?32}}</WRAP><WRAP column 92%>
+<panel type="info" title="Exercise 5.3.3.1 Frequency Divider"> <WRAP group><WRAP column 2%>{{fa>pencil?32}}</WRAP><WRAP column 92%>
 Investigate the simulation in <imgref pic052>.