DW EditSeite anzeigenÄltere VersionenLinks hierherAlles aus-/einklappenNach oben Diese Seite ist nicht editierbar. Sie können den Quelltext sehen, jedoch nicht verändern. Kontaktieren Sie den Administrator, wenn Sie glauben, dass hier ein Fehler vorliegt. CKG Editor ====== 5. Storage Elements ====== In the previous chapter we have had a look onto memory devices, which store data even when no voltage is applied. This is great for longterm storage, like measurement data, pictures or music. The clock frequency of the storage element are often much lower than the internal frequency of the processor / controller. By this, the processor has to wait for the stored information due to high access time. Therefore an controller-internal memory is advantageous. These are often called cache. Distinct storage elements have special properties, e.g. the written data changes the logic level of a pin ('foot') of the IC directly. We will now focus onto these controller-internal, fast memory, which consist of logic gates. The name flipflop stemms from the fact, that the smallest logic circuit for storing data has to store binary values. Therefore, it has to show one of two stable states, and can flip into the other one by an external interaction. ===== 5.1 Evolution of a Flipflop ===== ==== Flipflop as a Blackbox ==== In order to understand the wanted storage element, we will first look onto these element based on the IPO model (input–process–output). The process of the storage element is to store two different states. This property can be implemented via two inverting gates which are interconnected in a feedback loop. The simple setup would be with NOT gates as shown in <imgref pic01>. <WRAP><well> <imgcaption pic01|Storing two different states></imgcaption> \\ {{url>https://www.falstad.com/circuit/circuitjs.html?hideSidebar=true&ctz=CQAgjCAMB0mQrFWAmeyAcBmAnPX7IAWAdkIDZF5IRFDMaBTAWjDACgBJcMZcM6sMTJ9qo6JU7ghIZIQE8ZcqEkRhIbAO5ThYftsWjN3XrPm9dhrcmIml183vVbMmHXpfDTUSR4MybfmISXPYiIL4WyjCq6lysvJho+om8QTSS8SCEuvrZwmlqRpkpxuFk6N5agsJ5uXCVdWZlFU7JSdXNDR2uFZlylqX9gzmtoUNjI0a+Pf68Q63TSdPlDb7jATMLrlk5a-WjG0mhm5ITwmsjKukhhwnbJQXqAEYg6NjgyO-IalnwEM8yHDgTAQVzUQjwejqAAe3EQmCI4HQhHCkGIWUUIAANgB7ADmAEsAMYAHQAzjCZGR0Qi7ucEBjZNj8cTyewgA noborder}} </well></WRAP> Of course this simple elements misses inputs and outputs! Therefore we have to look into these now. The input of this element needs at least two inputs. Often the following two are used: * Set input: once this input is high, a $1$ is stored. This input is marked as $S$. * Reset input: once this input is low, a $0$ is stored. This input is marked as $R$. For the output also often two pins are shown. The pin $Q$ outputs the stored data directly. The pin $/Q$ outputs the inverted value. Based on this simple requirements we can create the truth table. * When $S=0$ and $R=0$, nothing changes and the outputs stay the same: $Q(n+1)=Q(n)$, $/Q(n+1)=/Q(n)$ * When $S=1$ and $R=0$, the stored information will be set: $Q(n+1)=1$, $/Q(n+1)=0$ * When $S=0$ and $R=1$, the stored information will be reset: $Q(n+1)=0$, $/Q(n+1)=1$ * When $S=1$ and $R=1$, it is unclear what to do. <WRAP> <imgcaption pic02| truth table for flipflop> </imgcaption> {{drawio>TTflipflop}} </WRAP> In <imgref pic02> the last input ($S=1$, $R=1$) reaches a not defined state. This state have to be investigated more later. ==== RS flip flop - Open the Blackbox ==== First, the storage device have get some inputs in order to change the stored stage. For This, a "switchable" NOT-gate is needed. Looking back to the chapter [[boolean_algebra#convertibility_of_gates| Boolean Algebra - Convertibility of Gates]], this can be achieved by NAND gates or NOR gates. \\ In <imgref pic03> a first approach is shown. <WRAP><well> <imgcaption pic03|storage device based on NAND or NOR></imgcaption> \\ {{url>https://www.falstad.com/circuit/circuitjs.html?ctz=CQAgzCAMB0mQrFWBGZBOALGATGgbABzZ54Ds6eE8kIiWtApgLSoBQA7iNqdiMqXi48+aXpA7gwg7BgKTpMqBLBSui7r3Rjlq5IXkjtnFYK1De2ReM4a1Gc1ww1rDjOuEYnS46rCjXVjqCUnIm4P4uYW72tn5GBp6hqtHeDmACaRGsyPDIDnpJpvp5vIjw2fAQsfphIXxcULQVJcIyhY5yJY3lOVUesgkDXWWsADL5eDTYcHyTDXkAZgCGADYAzgy0SuO22PDSM3vS9cvrm4jiAEaONMie4JRcJEoAsgYFIE6d+hbQ5W9hNqfSByIG-coADz46T4pFuz34EBi9gAGuIoZZOmB7OlNDDkSAAHIAQUJABEADprAAmDAAbgBLADGDFYGJwkkQUjyKjkBMJAHkAEpU2mMlmsa4yGjYnGPDDPdHQmJ4TSPYh0RwgFHINmfMCIDWfPAqvlagCauqhWE6pCRZFhggJ5qVyGxxrV9s1ih1erdpHAcNmwTtny1aLGrn2XBmGGjYhApw2W3EO2EUimMwzDRoSfOSmtYFCoYVAfSTotSqwdDwNfsCrNiktrAByQGX0+A3BLYMdQ7dW7QA noborder}} </well></WRAP> But how are the inputs $X_0$ and $X_1$ related to $S$ and $R$, as well as the outputs $Q$ and $/Q$ to $Y_0$ and $Y_1$? \\ In this introduction, only flip flops based on NOR gates are discussed - but flip flops are can also be build up with NAND gates. In <imgref pic04> such a NOR flip flop is shown. Compared to <imgref pic03> the outputs had to be rearranged in order to have the pins sorted as shown in the logic symbol (see <imgref pic05>) So let's analyze how this setup works! Therefore, the circuit in <imgref pic04> has to be analyzed: - Initially, $Q=0$ and the both inputs are $0$. This is due to the facts, that: - The upper NOR gate has also two $0$s as an input a outputs consequently $/Q=1$. - This $1$ is also an input to the lower NOR gate. - This respectively generates $Q=0$. This situation is stable. - When setting $S=1$ multiple things will happen successively: - At first, the upper NOR gate has a $1$ on the input, which results into a $0$ at the output, and on $/Q$. - With $/Q=0$ also both inputs of the lower NOR gate are $0$. - Therefore, the lower gate generates $Q=1$. - The stored data is also stable: - This means $Q=1$, even when going back to the initial state $S=0$ and $R=0$. - The upper NOR gate still has one input set to $1$ and consequently still generates a $0$. - The only way to clear $Q$ (i.e. to set $Q=0$) is by setting $R=1$ - This this input the lower NOR gate has a $1$ as an input and outputs $Q=0$. - By $Q=0$ the inputs of the upper NOR gate also both get $0$. - This results in $/Q=1$ The only problem (or better inconsistency) appears, when setting both inputs to $1$: * By this, both NOR gates generates $0$s * This on the one hand creates $Q=1$ and $/Q=1$, which is not consistent. This will get even more problematic: * Both gates show typically not the exact same behaviour in respect to setting their outputs on a sub-microsecond scale to the voltage comparable with the logic $1$ or $0$. * Therefore, once one will set the flip flop back to the initial state $S=0$ and $R=0$ both NOR gates compete to set their output to $1$. The faster one will win. * This results in an arbitrary behavior. <WRAP><well> <imgcaption pic04|The RS flip flop (based on NOR gates></imgcaption> \\ {{url>https://www.falstad.com/circuit/circuitjs.html?ctz=CQAgzCAMB0kKxVgRgCxMgTjGAHJA7JEmGnEiHJBSChHAKYC0SSAUAO4ioogBM+vLih68cOKBz6RxvFFW58BEzr2l8kANiky5y7YsELZVSJNUyMW8wb1HZQkbtNI4EI5v28P5QQjisXN2E+S09QnygKVgAPLjB5fBENLSR8fBo+HgA5AHkAJQAdAGcAMwAbAEsAB2LygHsq1gAjOJSMQV44DHBUCVj7eK00cEwM+zyYxXUeWnV0xxAAZVYAGQcRniV4kUiSgEMyovpqUzWjNSVrQSp9w+OEU1jsES9wOA77BYBFSbBOkYgYEoIyGmRAAHofgBZTIWLTbEJWPjQfww2QyDwIrxI3goswoOF8ezYvRXDy8YkeUwqAnqKzE0LUokiUJXRmsIA noborder}} </well></WRAP> <WRAP> <imgcaption pic05| The RS flipflop> </imgcaption> {{drawio>RSflipflop}} </WRAP> ==== D-Latch - Solving the Inconsistencies ==== ====== Examples ====== <WRAP><well> <imgcaption pic100|Shift Register with synchronous Load ></imgcaption> \\ {{url>http://www.falstad.com/circuit/circuitjs.html?hideSidebar=true&ctz=CQAgzCCMCmC0AcIAMA6ArAJgJwBYdaSTSRwHZCJiQ0QdK5JIAoAGVqUQx0Rw5A3hJ+UEADMAhgBsAztGrJWtXv25KhA9cjFTZ8pIuI4ViQ-0HChEmXJr62ZDMdqlHG4ZG3W9igGyEnfurmjh5Wura+YK6qPlFmmpY6NgpsaD6cqmmcwSJhyXbUYD5OaEXx7p7hCgCy7CbFvIiQxa7oTLV4QmlqUC38bbWm3abNwhgDzo7dDr1jE4HUxQujrWjtILFTS3Er-WuD6YuLTX3j+4XFw2W7Z0wASuCkxZAYQmB4UK8iIYS-6uh7LSoNZsMBPKCYcCQyCQxyJLwRUHgyDwIxgaGoiyVfJMFAgeAAIQAlgAXADKAAsiaISXdoABzInSEnQABOAHVSRSWAB7cQAEy0JigWBAAGEWABpWjfEC8gX4sYgMlEgB2G3AwgAGl1HKQRFqPGh9c8QFrHGBhR4tRA6DLrUYBJrrTQMBAQmbnjQPNb9aKhB4AJpCHDFfVCQMeMgaiMWqZaQMQMC2hNot4J72iuEgQPPH0J-XZoQAEQAYpIiQAHcs8ysAUUkAFsADrSSCtjCtsCtnDN1kAQVV-IA4uIWQ2W9I0K2fK3SH3ByOx9AJ634K2sK3IEg+wB5Vmj8dNrc76Tztt9gCSqoAbmyWazV9J11O9wfl0-IN2272252B0Oh4rsez5btObbdgBS5HpOzQdluvasmWFbVpItafp2bbtm256IchVY1vWIEolum7SK8PYLoBH4gRg2GMB2-6LkBT4vm6HaIfuLG0b+GCYSRrJcTRk4YLO5Hnhg05Qdxk5sWxs7ScJHZkZAZEYPOSHlgRaFESJ4FgKeYDYXhWmoehIHvF2mHopRikwV2YnJl2GnMUpoHSJaXaboJ772R5ZFgl2nG+cBk44MZmG8FR0GhWuPbfuF0UyT2v4GT2-74WZuk9oZCXgSZKGEU+3A9mJ+C2a5fnED255oO2dmxe5mCtqUb7JVO351T264+e1aDgWkLWIZVjUvsaLVSSNT5oC+UQtQpmVFSBaC-mQLVkYhvKMgAxruACuJKVgdT7eVtRK7QdR0kp+UlnRdh3HbRPV3ftD3XbRkEvZdj2TuNrJfW903-gDV1Pp5-08jtr2gyBdB9iDP1dp9kPndDiMecDKP3TDYUKQj71hRp+OfqdWNowTXY7hDUPfRTWHw2TtNPv+153qyD6sVuCms-ebKc+R9U8+zfMgS+eBXrevOPqLykS2zHMy1OPVCwrskOXLUv81Q7atqeOvkc2uuG6+F7wUbLVbsbnbmybO66+gxvgfr1vSHbJvO8bbtO1bnuO5bRum67-sGzb3tm0HFuBy7XvB9HftR77kce6Hwd677CcpxnEfuz7mfJ9nYchwXseJznAf62n4cx1n1f57XufFzX8d1836cu2c4cd0XXftw73d9734GD53A9W6PHbj+Rk892PQ+zyPc8T+BbvAvHK8O5H6-Tpvnsb7bu-b-v9uH8vB+O0w4VvOC8CIJaRiMB6hKkpS1K0gyTIPpyJLcnygrYQG8Eg5TigIA083pQEtWQMfSB2FMJgJAQbIB4DEHwP-gggBKCYEQOAbAgOyC4FYMwTg7ByCMEYIIcQoh+C8EIIodQpBtCaFoOYSQxhDDcHsNYRw1BXDdb8CXvwqeroBGYTOIIsRoiASSOEUI8RUiREKNkdIuRMiJECNPKvYBGi+62GgVovRujXY6KgUYgaJjNFrCAA noborder}} </well></WRAP> <WRAP><well> <imgcaption pic101|Shift Register with synchronous Load, Direction Bit and Sout></imgcaption> \\ {{url>http://www.falstad.com/circuit/circuitjs.html?hideSidebar=true&ctz=CQAgzCCMCmC0AcIAMA6SAmMkBsnsBZN8B2JfATmJAFYkaR8Jq5JIAoAGQaUXXjvw9wGEOiggAZgEMANgGdo9JJwaDR-VXSxixdafMXVkK2vnV1TwnckmyFSlSR0anV0eP32jyrtiR0+Oj8tETFIWwMHXzBnIJi3XQivYy5qbF4NNMRtd3DPQxSaMGxzIpKcsKSC5QBZbkQ0+qgSnRRqNjr8NUauuhx3dDaOmjIaEst+1vbO4jEe2eaBobrgsZBVydFl9fjG7HjNwemxhvH0xanh6mK165LDoYAlcGJ79C0uqHfxMP8--y2RiONlQ7S4YFeUGoYjA0Kh1jydmqbBQIHgACEAJYAFwAygALTESbGPaAAc0xcmx0AATgB1DgAeykABMACKYmk2RAtcIAYQ4AGkGD8QGyAJLPcjgdwcADyAEE2fRrLjxQA5EBUMxiXFygCqABUXiKIAAND5a8Rm8JgILWnTja0QdBiMzhM3u7LWoybD33PrWqglQMATRCVroofC6GDNlDOiY8YgkGlZij7qoECjvpj8ZKiHCUaoiTobIAYjJMQAHSuM6sAURkAFsADpySDt9DtsDt-CtmlMikAYzlAFdsdWJ0223JsAOh5jRxOp9iZ12BzUxzJsTWZNAAB609dyYjt+dyeDn9vUdvkdudmlbnd7w-HlsbjtIB+dr83u8Pt2g6MiO46TtOH6XguIFLmBq4npA340hWVa1jI9YId2UEdr2cj9shlY1nWjaQZA-Ydr+kC3nh0GgSuEGzjgtGwfRa6kY+z67tW+5HjSJ5Xh2F6QGegn-nI94dvhnGvrxCGUQJqYPgJ1ESe8zHLuBbGMWewF0ZpCFXgRqHESeakdiJ6C-lJ25cTx77aV2WGYI5Ymqfhi4afBpH3rpLH6ZBroDihRHoSRs7oORilyOg1HWS+3Fvnx3ldhesYpa5XaGR5cEMV2va+Z5uXRfORkhRhAUCc50USXFtmJaZuF2j2v5NXIKk9kB2WsaZOldf5s5NaVaHlQNTkiWAuG1TJ9lduN5FzRlciwupOVac1K3dZBYD4cFw1hT21FYD2F5TQlslbS15FYRe7VLb1MGFWtS3uq27bftFr3RW0G5dt9HafVhnaft2v3USDX3UUDcjvVD73g0cP0Qw+API8DAN-fDf2w6jH0faDiMI-9b04056Ng2TOMwyjeNIzThPY0TuOY+T+OM1TaOg2w+CIS8BaIF0hY3OEGI4gSRIkuSlLUvSTKshyXK-kCoOiMrv5hF2KsQ5rwK-n0N7a20Bu+hratG2butQBrTmG9bxttZb0Vm7bDt2zoyvO4rDtu1rHtvV7RsqBC9zwGYsJhCH7h6EiDgrAQoj9OkvAPGCvPx+UcKWS0Nj5A4QA noborder}} </well></WRAP> ====== further Links ====== * https://www.electronics-tutorials.ws/sequential/seq_1.html * https://www.electronics-tutorials.ws/counter/count_1.html