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electrical_engineering_and_electronics_1:block04 [2025/09/28 19:16] – angelegt mexleadminelectrical_engineering_and_electronics_1:block04 [2025/09/28 23:31] (aktuell) – mexleadmin
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 ===== Learning objectives ===== ===== Learning objectives =====
 <callout> <callout>
 +After this 90-minute block, you can
   * Identify nodes, branches, and (essential) loops in DC circuits and draw consistent reference arrows for $U$ and $I$ (passive/active sign conventions).   * Identify nodes, branches, and (essential) loops in DC circuits and draw consistent reference arrows for $U$ and $I$ (passive/active sign conventions).
   * State and apply **Kirchhoff’s Current Law (KCL)** at an arbitrary node and **Kirchhoff’s Voltage Law (KVL)** around a loop.    * State and apply **Kirchhoff’s Current Law (KCL)** at an arbitrary node and **Kirchhoff’s Voltage Law (KVL)** around a loop. 
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 Branches in electrical networks are also called two-terminal networks. Branches in electrical networks are also called two-terminal networks.
-Their behavior is described by current-voltage characteristics and explained in more detail in the chapter [[non-ideal_sources_and_two_terminal_networks]].+Their behavior is described by current-voltage characteristics and explained in more detail in [[block06]].
  
 In addition, another term is to be explained: \\ In addition, another term is to be explained: \\
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 In any node, the algebraic sum of currents is zero. All reference arrows are drawn either **into** or **out of** the node.   In any node, the algebraic sum of currents is zero. All reference arrows are drawn either **into** or **out of** the node.  
-\[+\begin{align*}
 \boxed{\sum_{\nu=1}^{n} I_\nu = 0} \quad \boxed{\sum_{\nu=1}^{n} I_\nu = 0} \quad
-\]+\end{align*} 
 Interpretation: the sum of currents flowing **into** a node equals the sum flowing **out of** that node → no net charge accumulation in steady DC.  Interpretation: the sum of currents flowing **into** a node equals the sum flowing **out of** that node → no net charge accumulation in steady DC. 
  
 **Sign rule used here.** If you write currents with reference arrows **toward** the node as positive, and **away** from the node as negative, KCL is $\sum I_x=0$. (Any one consistent choice is fine.)  **Sign rule used here.** If you write currents with reference arrows **toward** the node as positive, and **away** from the node as negative, KCL is $\sum I_x=0$. (Any one consistent choice is fine.) 
  
-**Worked example (KCL).**  +<panel type="info" title="Example / micro-exercise">
 At node $N$, suppose $I_1=2.00~{\rm A}$ and $I_2=0.50~{\rm A}$ flow **into** the node, and $I_3$ flows **out** of the node. With “into” positive: At node $N$, suppose $I_1=2.00~{\rm A}$ and $I_2=0.50~{\rm A}$ flow **into** the node, and $I_3$ flows **out** of the node. With “into” positive:
-\[+\begin{align*}
 I_1 + I_2 - I_3 = 0 \Rightarrow I_3 = 2.50~{\rm A}. I_1 + I_2 - I_3 = 0 \Rightarrow I_3 = 2.50~{\rm A}.
-\]+\end{align*} 
 Units check: $[I]={\rm A}$ on every term, so the sum is consistent. Units check: $[I]={\rm A}$ on every term, so the sum is consistent.
 +</panel>
  
 <callout color="gray" icon="fa fa-check"> <callout color="gray" icon="fa fa-check">
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 __In general__: the equivalent resistance of a parallel circuit is always smaller than the smallest resistance. __In general__: the equivalent resistance of a parallel circuit is always smaller than the smallest resistance.
  
-Especially for two parallel resistors $R_1$ and $R_2$ applies: $R_{\rm eq}= \large{{R_1 \cdot R_2}\over{R_1 + R_2}}$+Especially for two parallel resistors $R_1$ and $R_2$ applies:  
 + 
 +\begin{align*} 
 +\boxed{R_{\rm eq}= R_1 || R_2 = \large{{R_1 \cdot R_2}\over{R_1 + R_2}}  } 
 +\end{align*} 
  
 ==== Current divider ==== ==== Current divider ====
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 The rule states that the currents $I_1, ... I_n$ on parallel resistors $R_1, ... R_n$ behave just like their conductances $G_1, ... G_n$ through which the current flows. \\ The rule states that the currents $I_1, ... I_n$ on parallel resistors $R_1, ... R_n$ behave just like their conductances $G_1, ... G_n$ through which the current flows. \\
  
-$\large{{I_1}\over{I_{\rm res}}} = {{G_1}\over{G_{\rm res}}}$  +\begin{align*} 
- +\large{{I_1}\over{I_{\rm res}}} = {{G_1}\over{G_{\rm res}}} 
-$\large{{I_1}\over{I_2}} = {{G_1}\over{G_2}}$+\large{{I_1}\over{I_2}} = {{G_1}\over{G_2}} 
 +\end{align*}
  
 The rule also be derived from Kirchhoff's current law: \\ The rule also be derived from Kirchhoff's current law: \\
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 ~~PAGEBREAK~~ ~~CLEARFIX~~ ~~PAGEBREAK~~ ~~CLEARFIX~~
- 
 ==== Kirchhoff’s Voltage Law (KVL) ==== ==== Kirchhoff’s Voltage Law (KVL) ====
  
 Around any closed loop, the algebraic sum of voltages is zero: Around any closed loop, the algebraic sum of voltages is zero:
-\[+\begin{align*}
 \boxed{\sum_{\nu=1}^{n} U_\nu = 0} \quad  \boxed{\sum_{\nu=1}^{n} U_\nu = 0} \quad 
-\]+\end{align*} 
 Equivalently: the sum of rises equals the sum of drops along the chosen loop direction. The result does **not** depend on the specific path between two nodes.  Equivalently: the sum of rises equals the sum of drops along the chosen loop direction. The result does **not** depend on the specific path between two nodes. 
  
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 <panel type="info" title="Example / micro-exercise"> <panel type="info" title="Example / micro-exercise">
 Series loop with source $U_{\rm s}=12.0~{\rm V}$, resistors $R_1=3.0~\Omega$, $R_2=5.0~\Omega$. With passive sign convention across both resistors and loop direction from the $+$ of the source: Series loop with source $U_{\rm s}=12.0~{\rm V}$, resistors $R_1=3.0~\Omega$, $R_2=5.0~\Omega$. With passive sign convention across both resistors and loop direction from the $+$ of the source:
-\[+\begin{align*}
 -U_{\rm s} + U_{R_1} + U_{R_2} = 0, \quad U_{R_k} = R_k I. -U_{\rm s} + U_{R_1} + U_{R_2} = 0, \quad U_{R_k} = R_k I.
-\] +\end{align*} 
-Thus $I = \frac{U_{\rm s}}{R_1+R_2} = \frac{12.0~{\rm V}}{8.0~\Omega}=1.50~{\rm A}$,   + 
-$U_{R_1}=4.50~{\rm V}$, $U_{R_2}=7.50~{\rm V}$, and $-12.0~{\rm V}+4.50~{\rm V}+7.50~{\rm V}=0$. (Check: volts add algebraically to $0$.) +Thus  \\ 
 +$I = \frac{U_{\rm s}}{R_1+R_2} = \frac{12.0~{\rm V}}{8.0~\Omega}=1.50~{\rm A}$ \\ 
 +$U_{R_1}=4.50~{\rm V}$, $U_{R_2}=7.50~{\rm V}$ \\ 
 +$-12.0~{\rm V}+4.50~{\rm V}+7.50~{\rm V}=0$. (Check: volts add algebraically to $0$.) 
 </panel> </panel>
  
 ~~PAGEBREAK~~ ~~CLEARFIX~~ ~~PAGEBREAK~~ ~~CLEARFIX~~
 +=== Series circuit of resistors ===
 +
 +<WRAP>
 +<imgcaption BildNr13 | series circuit>
 +</imgcaption>
 +{{drawio>Reihenschaltung.svg}}
 +</WRAP>
 +
 +Using Kirchhoff's voltage law, the total resistance of a series circuit (in German: //Reihenschaltung//, see <imgref BildNr13>) can be easily determined:
 +
 +\begin{align*}
 +U_1 + U_2 + ... + U_n = U_{\rm res}
 +R_1 \cdot I_1 + R_2 \cdot I_2 + ... + R_n \cdot I_n = R_{\rm eq} \cdot I 
 +\end{align*}
 +
 +Since in a series circuit, the current through all resistors must be the same - i.e. $I_1 = I_2 = ... = I$ - it follows that:
 +
 +\begin{align*}
 +R_1 + R_2 + ... + R_n = R_{\rm eq} =  \sum_{x=1}^{n} R_x 
 +\end{align*}
 +
 +
 +__In general__: The equivalent resistance of a series circuit is always greater than the greatest resistance.
  
 ===== From laws to tools (preview) ===== ===== From laws to tools (preview) =====
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   * **Series**: same current through all series elements $\Rightarrow$ voltages add, $R_{\rm eq}=R_1+R_2+\dots$.   * **Series**: same current through all series elements $\Rightarrow$ voltages add, $R_{\rm eq}=R_1+R_2+\dots$.
   * **Parallel**: same voltage across all parallel elements $\Rightarrow$ currents add, $G_{\rm eq}=G_1+G_2+\dots$.   * **Parallel**: same voltage across all parallel elements $\Rightarrow$ currents add, $G_{\rm eq}=G_1+G_2+\dots$.
-  * **Dividers** and **bridge** behavior follow from the same laws. (We will formalize these in **Block 05**.) +  * **Dividers** and **bridge** behavior follow from the same laws. (We will formalize these in [[Block05]].) 
  
 For orientation, the short slides you cross-check with present the same sequence: KCL/KVL → resistive networks → (later) real sources and two-port models. For orientation, the short slides you cross-check with present the same sequence: KCL/KVL → resistive networks → (later) real sources and two-port models.
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 </WRAP> </WRAP>
 </WRAP></WRAP></panel>  </WRAP></WRAP></panel> 
- 
-<panel type="info" title="Exercise 4.2 KCL at a node (with simulator)"> <WRAP group><WRAP column 2%>{{fa>pencil?32}}</WRAP><WRAP column 92%> 
-Open the linked circuit. Choose one **principal node**, add current arrows (all into the node), and write KCL. Then read two branch currents from the sim and solve for the third.   
-<WRAP> 
-<imgcaption BildNr5 | Example of a circuit> 
-</imgcaption> \\ 
-{{url>https://www.falstad.com/circuit/circuitjs.html?running=false&ctz=CQAgjCAMB0l3BWcMBMcUHYMGZIA4UA2ATmIxEJRCQBZsAoAJxDqsJvA0JGO8hBRpITTt14hsacMSr9Mw5pP5gZEwnnA0OyhHBGsKHGuJQI+LDHubHup7kumyQBKxKkqqNMPfVRwQhRYTMxZvNQ1+dUCUGmVVbzlYvzAAkQcPASTsbHMzVxj+bO4vHwiLEQKJHP8NTCcweHoANxqBDCowLh5zfiT+JH4YMARiYeM6SBl6AGUBPFr8TLlF5RAAMwBDABsAZwBTPxR6AHc5hY101WikwQ4EtqdsYmFT+8qU2vaoE-BCOS+Pg9vgAPAQjaQQTBIFRGTIgab0UHYGjkFIQbAIDQpWFSI5Ip7gFISFGE2gSfgASXo2Es4U0HGweDuKCxfheEiZrQM7BBbTuxFqeCQaAgHHc9CAA noborder}} 
-</WRAP> 
-*Strategy.* Fix “into node = positive”, then sum currents to $0$; rearrange to get the unknown.   
-*Solution check.* Toggle the switch and observe sign changes; explain with your chosen reference arrows. 
-</WRAP></WRAP></panel> 
  
  
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 <panel type="info" title="Exercise 4.3 KVL in a loop (source + two resistors)"> <WRAP group><WRAP column 2%>{{fa>pencil?32}}</WRAP><WRAP column 92%> <panel type="info" title="Exercise 4.3 KVL in a loop (source + two resistors)"> <WRAP group><WRAP column 2%>{{fa>pencil?32}}</WRAP><WRAP column 92%>
-Sketch a loop with $U_{\rm s}=5.00~{\rm V}$, $R_1=1.00~{\rm k\Omega}$, $R_2=1.00~{\rm k\Omega}$. Draw passive arrows across both resistors and choose clockwise loop direction.   +Sketch a loop with $U_{\rm s}=5.00~{\rm V}$, $R_1=1.00~{\rm k\Omega}$, $R_2=1.00~{\rm k\Omega}$. Draw passive arrows across both resistors and choose clockwise loop direction.  \\ 
-Write KVL, solve $I$, then compute $U_{R_1}$ and $U_{R_2}$. Confirm that algebraic sum equals $0~{\rm V}$.  +Write KVL, solve $I$, then compute $U_{R_1}$ and $U_{R_2}$. Confirm that algebraic sum equals $0~{\rm V}$.  \\
 *Expected:* $I=2.50~{\rm mA}$, $U_{R_1}=2.50~{\rm V}$, $U_{R_2}=2.50~{\rm V}$. *Expected:* $I=2.50~{\rm mA}$, $U_{R_1}=2.50~{\rm V}$, $U_{R_2}=2.50~{\rm V}$.
 </WRAP></WRAP></panel> </WRAP></WRAP></panel>
  
-<panel type="info" title="Exercise 4.4 (optional) Current divider intuition"> <WRAP group><WRAP column 2%>{{fa>pencil?32}}</WRAP><WRAP column 92%> + 
-Use the sim to see **parallel** currents add and split. Move the slider and observe how the larger conductance branch takes the larger share.   +<panel type="info" title="Exercise 2.4.3 Three Resistors"> <WRAP group><WRAP column 2%>{{fa>pencil?32}}</WRAP><WRAP column 92%> 
-<WRAP> + 
-<imgcaption BildNr85| Current divider> +Three equal resistors of $20~k\Omega$ each are given. \\ 
-</imgcaption> \\ +Which values are realizable by the arbitrary interconnection of one to three resistors?\\ 
-{{url>https://www.falstad.com/circuit/circuitjs.html?running=false&ctz=CQAgjCAMB0l3BWKsBMA2AzAgnAdjBgBxhgK7q64gKTXWQBQATiCgmuLh2xxpACxRwcBmHKt2nbpLApCQqkiS0V0JADUA9gBsALgEMA5gFMGhibwzTeCFFAYB3CyD6CeLq+GYvbUn3dchMHhHfxcBMIxPMDNIzywA30YnQLEbOzT7J3dM1K4s50ywNFpMxhZi2hQUQUrnUpCnOtSSjw4Y82bo1oSCupyeiMYAZ3BW6trWsvAQADN9bWHTIA noborder}} +<button size="xs" type="link" collapse="Loesung_2_4_3_1_Lösungsweg">{{icon>eye}} Solution</button><collapse id="Loesung_2_4_3_1_Lösungsweg" collapsed="true"> 
-</WRAP> +The resistors can be connected in series: 
-Then, write KCL at the top node, use $U=U_{ab}$ common to both branches, and derive $\tfrac{I_1}{I_2}=\tfrac{G_1}{G_2}$ (dimensionless).   +\begin{equation*} 
-</WRAP></WRAP></panel> +R_{\rm series} = 3\cdot R = 3\cdot20~k\Omega 
 +\end{equation*} 
 +The resistors can also be connected in parallel: 
 +\begin{equation*} 
 +R_{\rm parallel} = \frac{R}{3} = \frac{20~k\Omega}{3} 
 +\end{equation*} 
 +On the other hand, they can also be connected in a way that two of them are in parallel and those are in series to the third one: 
 +\begin{equation*} 
 +R_{\rm res} = R + \frac{R\cdot R}{R+R} = \frac{3}{2}R = \frac{3}{2} \cdot 20~k\Omega 
 +\end{equation*} 
 +</collapse> 
 +<button size="xs" type="link" collapse="Loesung_2_4_3_2_Lösungsweg">{{icon>eye}} Final values</button><collapse id="Loesung_2_4_3_2_Lösungsweg" collapsed="true"> 
 +\begin{equation*} 
 +R_{series} = 60~k\Omega\qquad R_{\rm parallel} = 6.7~k\Omega\qquad R_{\rm res} = 30~k\Omega 
 +\end{equation*} 
 +</collapse> 
 +</WRAP></WRAP></panel>
  
 ~~PAGEBREAK~~ ~~CLEARFIX~~ ~~PAGEBREAK~~ ~~CLEARFIX~~
  
-===== Media & references from the notes ===== +===== Embedded resources =====
-<WRAP> +
-{{wp>Kirchhoff's circuit laws}} +
-{{youtube>d0O-KUKP4nM}} +
-</WRAP> +
  
-<WRAP>+<WRAP column half>
 Explanation of the different network structures \\ Explanation of the different network structures \\
 (Graphs and trees are only needed in later chapters) (Graphs and trees are only needed in later chapters)
- 
 {{youtube>-82UNytyrCQ}} {{youtube>-82UNytyrCQ}}
 </WRAP> </WRAP>
  
- +<WRAP column half>
-<WRAP>+
 Reshaping circuits Reshaping circuits
 {{youtube>PnzijvMQmE8}} {{youtube>PnzijvMQmE8}}
 </WRAP> </WRAP>
  
-<WRAP> +<WRAP column half>
-Explanation of the different network structures \\ +
-We do not need graphs and trees  +
-{{youtube>-82UNytyrCQ}} +
-</WRAP> +
- +
-<WRAP>+
 {{wp>Kirchhoff's circuit laws}} {{wp>Kirchhoff's circuit laws}}
 {{youtube>d0O-KUKP4nM}} {{youtube>d0O-KUKP4nM}}
 </WRAP>  </WRAP> 
  
-<WRAP>+<WRAP column half>
 Derivation of the current divider with examples Derivation of the current divider with examples
 {{youtube>VojwBoSHc8U}} {{youtube>VojwBoSHc8U}}
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 ~~PAGEBREAK~~ ~~CLEARFIX~~ ~~PAGEBREAK~~ ~~CLEARFIX~~
- +===== Summary =====
-===== Summary (takeaways) =====+
   * **KCL:** sum of signed currents at any node is $0$ (charge does not pile up in steady DC).     * **KCL:** sum of signed currents at any node is $0$ (charge does not pile up in steady DC).  
   * **KVL:** sum of signed voltages around any loop is $0$ (potential differences are path-independent).     * **KVL:** sum of signed voltages around any loop is $0$ (potential differences are path-independent).  
   * **Conventions matter:** fix passive/active sign conventions once, then *stay consistent*.     * **Conventions matter:** fix passive/active sign conventions once, then *stay consistent*.  
   * **Next:** apply KCL/KVL to build series/parallel laws, dividers, and bridges (Block 05); then model real sources and two-port equivalents.    * **Next:** apply KCL/KVL to build series/parallel laws, dividers, and bridges (Block 05); then model real sources and two-port equivalents. 
- 
-===== What’s next (preview of Block 05) ===== 
-Series/parallel combinations and divider rules derived systematically from KCL/KVL; bridge circuits and balance condition. (Have your calculator ready; units on **every** numerical result.) 
  
 ~~PAGEBREAK~~ ~~CLEARFIX~~ ~~PAGEBREAK~~ ~~CLEARFIX~~
-