Block 04 — Kirchhoff’s laws

Learning objectives

90-minute plan

1. Warm-up (10 min): What is a “node”? what is a “mesh”? quick sketch-and-label drill.
2. Core concepts (40 min): reference arrows & sign conventions → KCL at a node → KVL in a loop → dimensional check.
3. Worked examples (20 min): one KCL node solve; one KVL loop solve with a source and two resistors.
4. Guided practice (15–20 min): short tasks (incl. sims/drawings below).
5. Wrap-up (5 min): checklist, common pitfalls, outlook to Block 05 (series/parallel, dividers, bridge).

Core Content

Nodes, Branches, and Loops

Electrical circuits typically have the structure of networks. Networks consist of two elementary structural elements:

1. Branches (German: Zweige): Connections between two nodes.
2. Node (German: Knoten): Connection „point“ of several branches.

Please note in the case of electrical circuits, we will use the following definition:

1. Branches contain at least one component.
2. Nodes connect more than two branches. Since the wire in a circuit diagram is an ideal conductor, all connected wires to a node are at the same voltage level. Therefore the node in the circuit diagram can also be spatially extended by the wires.

Sometimes there is a differentiation between „simple nodes“ (only connecting 2 branches) and „principal nodes“ (connecting more than 2 branches). We will in the following often only mark the connection of more than two branches with a node.

Branches in electrical networks are also called two-terminal networks. Their behavior is described by current-voltage characteristics and explained in more detail in block06.

In addition, another term is to be explained:

A loop begins and ends at the same node and runs over at least one further node.

Since a voltmeter can also be present as a component between two nodes, it is also possible to close a loop by a drawn voltage arrow (cf. $U_1$ in Abbildung 2).

Please keep in mind, that usually the entire behavior of networked circuits almost always changes when a change occurs in one branch or at one node. This is in contrast to other cause-effect relationships, but comparable to changes in other larger networks, e.g. a traffic jam in the road network, due to which other roads experience a higher load. For electrical engineering, this means that in the case of changing circuits, the focus is often on determining the interrelationships (formulas, current-voltage characteristics) and not on a single numerical value.

Reshaping Circuits

With the knowledge of nodes, branches, and meshes, circuits can be simplified. Circuits can be reshaped arbitrarily as long as all branches remain at the same nodes after reshaping The Abbildung 3 shows how such a transformation is possible.

For practical tasks, repeated trial and error can be useful. It is important to check afterward that the same components are connected to each node as before the transformation.

Kirchhoff’s Current Law (KCL)

In any node, the algebraic sum of currents is zero. All reference arrows are drawn either into or out of the node. \begin{align*} \boxed{\sum_{\nu=1}^{n} I_\nu = 0} \quad \end{align*}

Interpretation: the sum of currents flowing into a node equals the sum flowing out of that node → no net charge accumulation in steady DC.

Sign rule used here. If you write currents with reference arrows toward the node as positive, and away from the node as negative, KCL is $\sum I_x=0$. (Any one consistent choice is fine.)

Parallel circuit of resistors

From Kirchhoff's current law, the total resistance for resistors connected in parallel can be derived (Abbildung 5):

Since the same voltage $U_{ab}$ is dropped across all resistors, using Kirchhoff's current law:

$\large{{U_{ab}}\over{R_1}}+ {{U_{ab}}\over{R_2}}+ ... + {{U_{\rm ab}}\over{R_n}}= {{U_{\rm ab}}\over{R_{\rm eq}}}$

$\rightarrow \large{{{1}\over{R_1}}+ {{1}\over{R_2}}+ ... + {{1}\over{R_n}}= {{1}\over{R_{\rm eq}}} = \sum_{x=1}^{n} {{1}\over{R_x}}}$

Thus, for resistors connected in parallel, the equivalent conductance $G_{\rm eq}$ (German: Ersatzleitwert) is the sum of the individual conductances: $G_{\rm eq} = \sum_{x=1}^{n} {G_x}$

In general: the equivalent resistance of a parallel circuit is always smaller than the smallest resistance.

Especially for two parallel resistors $R_1$ and $R_2$ applies:

\begin{align*} \boxed{R_{\rm eq}= R_1 || R_2 = \large{{R_1 \cdot R_2}\over{R_1 + R_2}} } \end{align*}

Current divider

The current divider rule shows in which way an incoming current on a node will be divided into two outgoing branches. The rule states that the currents $I_1, ... I_n$ on parallel resistors $R_1, ... R_n$ behave just like their conductances $G_1, ... G_n$ through which the current flows.

\begin{align*} \large{{I_1}\over{I_{\rm res}}} = {{G_1}\over{G_{\rm res}}} \large{{I_1}\over{I_2}} = {{G_1}\over{G_2}} \end{align*}

The rule also be derived from Kirchhoff's current law:

1. The voltage drop $U$ on parallel resistors $R_1, ... R_n$ is the same.
2. When $U_1 = U_2 = ... = U$, then the following equation is also true: $R_1 \cdot I_1 = R_2 \cdot I_2 = ... = R_{\rm eq} \cdot I_{\rm res}$.
   
3. Therefore, we get with the conductance: ${{I_1} \over {G_1}} = {{I_2} \over {G_2}}= ... = {{I_{\rm eq}} \over {G_{\rm res}}}$

Kirchhoff’s Voltage Law (KVL)

Around any closed loop, the algebraic sum of voltages is zero: \begin{align*} \boxed{\sum_{\nu=1}^{n} U_\nu = 0} \quad \end{align*}

Equivalently: the sum of rises equals the sum of drops along the chosen loop direction. The result does not depend on the specific path between two nodes.

Sign rule used here. Choose a loop direction (often clockwise). A voltage arrow aligned with the loop direction is added; opposed to it is subtracted. (Source polarities must respect the active/passive conventions fixed earlier.)

Series circuit of resistors

Using Kirchhoff's voltage law, the total resistance of a series circuit (in German: Reihenschaltung, see Abbildung 7) can be easily determined:

\begin{align*} U_1 + U_2 + ... + U_n = U_{\rm res} R_1 \cdot I_1 + R_2 \cdot I_2 + ... + R_n \cdot I_n = R_{\rm eq} \cdot I \end{align*}

Since in a series circuit, the current through all resistors must be the same - i.e. $I_1 = I_2 = ... = I$ - it follows that:

\begin{align*} R_1 + R_2 + ... + R_n = R_{\rm eq} = \sum_{x=1}^{n} R_x \end{align*}

In general: The equivalent resistance of a series circuit is always greater than the greatest resistance.

From laws to tools (preview)

KCL and KVL immediately yield:

• Series: same current through all series elements $\Rightarrow$ voltages add, $R_{\rm eq}=R_1+R_2+\dots$.
• Parallel: same voltage across all parallel elements $\Rightarrow$ currents add, $G_{\rm eq}=G_1+G_2+\dots$.
• Dividers and bridge behavior follow from the same laws. (We will formalize these in Block05.)

For orientation, the short slides you cross-check with present the same sequence: KCL/KVL → resistive networks → (later) real sources and two-port models.

Common pitfalls

• Mixed conventions: do not swap passive/active mid-solution. Fix reference arrows once, then stick to them.
• Sign slips: in KVL, mark loop direction on the drawing; in KCL, decide “in is $+$” (or “out is $+$”) and keep it for *all* terms.
• Units: always write ${\rm A}$ for currents and ${\rm V}$ for voltages in interim and final results.

Exercises

Embedded resources

Summary

• KCL: sum of signed currents at any node is $0$ (charge does not pile up in steady DC).
• KVL: sum of signed voltages around any loop is $0$ (potential differences are path-independent).
• Conventions matter: fix passive/active sign conventions once, then *stay consistent*.
• Next: apply KCL/KVL to build series/parallel laws, dividers, and bridges (Block 05); then model real sources and two-port equivalents.