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| Beide Seiten der vorigen Revision Vorhergehende Überarbeitung Nächste Überarbeitung | Vorhergehende Überarbeitung | ||
| electrical_engineering_and_electronics_1:block04 [2025/09/28 23:31] – mexleadmin | electrical_engineering_and_electronics_1:block04 [2026/01/10 13:24] (aktuell) – mexleadmin | ||
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| Zeile 1: | Zeile 1: | ||
| ====== Block 04 — Kirchhoff’s laws ====== | ====== Block 04 — Kirchhoff’s laws ====== | ||
| - | ===== Learning objectives | + | ===== 4.0 Intro ===== |
| + | |||
| + | ==== 4.0.1 Learning Objectives | ||
| < | < | ||
| After this 90-minute block, you can | After this 90-minute block, you can | ||
| Zeile 10: | Zeile 12: | ||
| </ | </ | ||
| - | ===== 90-minute | + | ==== 4.0.2 Preparation at Home ==== |
| + | |||
| + | As always: | ||
| + | * Please read through the following chapter. | ||
| + | * Also here, there are some clips for more clarification under ' | ||
| + | |||
| + | For checking your understanding please do the following exercises: | ||
| + | * 2.3.3 (1) | ||
| + | * 2.4.3 | ||
| + | |||
| + | ==== 4.0.3 90-minute | ||
| - Warm-up (10 min): What is a “node”? what is a “mesh”? quick sketch-and-label drill. | - Warm-up (10 min): What is a “node”? what is a “mesh”? quick sketch-and-label drill. | ||
| - Core concepts (40 min): reference arrows & sign conventions → KCL at a node → KVL in a loop → dimensional check. | - Core concepts (40 min): reference arrows & sign conventions → KCL at a node → KVL in a loop → dimensional check. | ||
| Zeile 18: | Zeile 30: | ||
| ~~PAGEBREAK~~ ~~CLEARFIX~~ | ~~PAGEBREAK~~ ~~CLEARFIX~~ | ||
| - | ===== Core Content | + | ===== 4.1 Core Content |
| - | ==== Nodes, Branches, and Loops ==== | + | ==== 4.1.1 Nodes, Branches, and Loops ==== |
| Electrical circuits typically have the structure of networks. Networks consist of two elementary structural elements: | Electrical circuits typically have the structure of networks. Networks consist of two elementary structural elements: | ||
| Zeile 59: | Zeile 71: | ||
| ~~PAGEBREAK~~ ~~CLEARFIX~~ | ~~PAGEBREAK~~ ~~CLEARFIX~~ | ||
| - | ==== Reshaping Circuits ==== | + | ==== 4.1.2 Reshaping Circuits ==== |
| With the knowledge of nodes, branches, and meshes, circuits can be simplified. | With the knowledge of nodes, branches, and meshes, circuits can be simplified. | ||
| Zeile 76: | Zeile 88: | ||
| ~~PAGEBREAK~~ ~~CLEARFIX~~ | ~~PAGEBREAK~~ ~~CLEARFIX~~ | ||
| - | ==== Kirchhoff’s Current Law (KCL) ==== | + | ==== 4.1.3 Kirchhoff’s Current Law (KCL) ==== |
| <WRAP right> | <WRAP right> | ||
| Zeile 107: | Zeile 119: | ||
| ~~PAGEBREAK~~ ~~CLEARFIX~~ | ~~PAGEBREAK~~ ~~CLEARFIX~~ | ||
| - | ==== Parallel circuit of resistors ==== | + | ==== 4.1.4 Parallel circuit of resistors ==== |
| From Kirchhoff' | From Kirchhoff' | ||
| Zeile 117: | Zeile 129: | ||
| </ | </ | ||
| - | Since the same voltage $U_{ab}$ is dropped across all resistors, using Kirchhoff' | + | Since the same voltage $U_{\rm ab}$ is dropped across all resistors, using Kirchhoff' |
| - | $\large{{U_{ab}}\over{R_1}}+ {{U_{ab}}\over{R_2}}+ ... + {{U_{\rm ab}}\over{R_n}}= {{U_{\rm ab}}\over{R_{\rm eq}}}$ | + | $\large{{U_{\rm ab}}\over{R_1}}+ {{U_{\rm ab}}\over{R_2}}+ ... + {{U_{\rm ab}}\over{R_n}}= {{U_{\rm ab}}\over{R_{\rm eq}}}$ |
| $\rightarrow \large{{{1}\over{R_1}}+ {{1}\over{R_2}}+ ... + {{1}\over{R_n}}= {{1}\over{R_{\rm eq}}} = \sum_{x=1}^{n} {{1}\over{R_x}}}$ | $\rightarrow \large{{{1}\over{R_1}}+ {{1}\over{R_2}}+ ... + {{1}\over{R_n}}= {{1}\over{R_{\rm eq}}} = \sum_{x=1}^{n} {{1}\over{R_x}}}$ | ||
| Zeile 134: | Zeile 146: | ||
| - | ==== Current divider ==== | + | ==== 4.1.5 Current divider ==== |
| The current divider rule shows in which way an incoming current on a node will be divided into two outgoing branches. | The current divider rule shows in which way an incoming current on a node will be divided into two outgoing branches. | ||
| Zeile 150: | Zeile 162: | ||
| ~~PAGEBREAK~~ ~~CLEARFIX~~ | ~~PAGEBREAK~~ ~~CLEARFIX~~ | ||
| - | ==== Kirchhoff’s Voltage Law (KVL) ==== | + | ==== 4.1.6 Kirchhoff’s Voltage Law (KVL) ==== |
| Around any closed loop, the algebraic sum of voltages is zero: | Around any closed loop, the algebraic sum of voltages is zero: | ||
| Zeile 205: | Zeile 217: | ||
| __In general__: The equivalent resistance of a series circuit is always greater than the greatest resistance. | __In general__: The equivalent resistance of a series circuit is always greater than the greatest resistance. | ||
| - | ===== From laws to tools (preview) | + | ==== 4.1.7 From laws to tools (preview) ==== |
| KCL and KVL immediately yield: | KCL and KVL immediately yield: | ||
| Zeile 216: | Zeile 228: | ||
| ~~PAGEBREAK~~ ~~CLEARFIX~~ | ~~PAGEBREAK~~ ~~CLEARFIX~~ | ||
| - | ===== Common pitfalls ===== | + | ===== 4.2 Common pitfalls ===== |
| * **Mixed conventions**: | * **Mixed conventions**: | ||
| * **Sign slips**: in KVL, mark loop direction on the drawing; in KCL, decide “in is $+$” (or “out is $+$”) and keep it for *all* terms. | * **Sign slips**: in KVL, mark loop direction on the drawing; in KCL, decide “in is $+$” (or “out is $+$”) and keep it for *all* terms. | ||
| Zeile 222: | Zeile 234: | ||
| ~~PAGEBREAK~~ ~~CLEARFIX~~ | ~~PAGEBREAK~~ ~~CLEARFIX~~ | ||
| - | ===== Exercises ===== | + | ===== 4.3 Exercises ===== |
| <panel type=" | <panel type=" | ||
| Zeile 251: | Zeile 263: | ||
| </ | </ | ||
| - | <panel type=" | + | |
| - | Label nodes (degree $\ge 3$), branches, and at least two distinct loops. | + | |
| - | < | + | |
| - | < | + | |
| - | </ | + | |
| - | {{drawio> | + | |
| - | </ | + | |
| - | </ | + | |