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5. Storage Elements

In the previous chapter we have had a look onto memory devices, which store data even when no voltage is applied. This is great for longterm storage, like measurement data, pictures or music. The clock frequency of the storage element are often much lower than the internal frequency of the processor / controller. By this, the processor has to wait for the stored information due to high access time.

Therefore an controller-internal memory is advantageous. These are often called cache. Distinct storage elements have special properties, e.g. the written data changes the logic level of a pin ('foot') of the IC directly. We will now focus onto these controller-internal, fast memory, which consist of logic gates.

In order to understand the wanted storage element, we will first look onto thes element base on the IPO model (input–process–output).

The input of this element needs at least two inputs. Often the following two are used:

  • Set input: once this input is high, a $1$ is stored. This input is marked as $S$.
  • Reset input: once this input is low, a $0$ is stored. This input is marked as $R$.

For the output also often two pins are shown. The pin $Q$ outputs the stored data directly. The pin $/Q$ outputs the inverted value.

We can transform this simple requirements into a truth table

Abb. ##: Simulation of a PAL

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